Patents by Inventor Ping-Chi Cheng

Ping-Chi Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11984649
    Abstract: A wearable device includes a conducting frame, a circuit board, and a grounding member. The conducting frame includes a first part and a second part that are separated. The circuit board has a system grounding surface and is disposed inside the conducting frame. The grounding member is disposed inside the conducting frame and connected to the first part. The first part and the grounding member are formed as a first antenna. The first part has a first feeding terminal. The grounding member has a first grounding terminal, and the first grounding terminal is connected to the system grounding surface of the circuit board. The second part is formed as a second antenna. The second antenna has a second feeding terminal, a second grounding terminal, and a third grounding terminal. The second and the third grounding terminals are connected to the system grounding surface of the circuit board.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: May 14, 2024
    Assignee: PEGATRON CORPORATION
    Inventors: Kuo-Chi Cheng, Po-Yen Lai, Ping-Hung Lu
  • Publication number: 20240087644
    Abstract: A forming operation of resistive memory device is provided. The operation includes: applying a pre-forming gate voltage and a pre-forming bit line voltage to a target memory cell; performing a dense switching forming operation, wherein the dense switching forming operation includes alternately performing dense set operations and dense reset operations on the target memory cell, wherein the dense set operation includes applying a dense switching gate voltage and a dense set bit line voltage; and performing a normal set operation on the target memory cell, wherein the normal set operation includes applying a normal set gate voltage and a normal set bit line voltage to the target memory cell, the normal set gate voltage is greater than the pre-forming gate voltage and the dense switching gate voltage, and the normal set bit line voltage is less than the pre-forming bit line voltage and the dense set bit line voltage.
    Type: Application
    Filed: August 29, 2023
    Publication date: March 14, 2024
    Applicant: Winbond Electronics Corp.
    Inventors: I-Hsien Tseng, Lung-Chi Cheng, Ju-Chieh Cheng, Jun-Yao Huang, Ping-Kun Wang
  • Patent number: D763476
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: August 9, 2016
    Assignee: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventor: Ping-Chi Cheng