Abstract: A data capture device including a signal processing unit, a frequency locked circuit and a match circuit is provided. The signal processing unit converts a radio frequency signal to a return-to-zero signal. The frequency locked circuit estimates a minimum interval length by the return-to-zero signal in a plurality of detecting periods, and generates an enable signal according to the minimum interval length and the return-to-zero signal. The frequency locked circuit determines whether to calibrate the enable signal according to a distribution of a plurality of enable pulses in the enable signal to generate a sampling signal. The match circuit samples the return-to-zero signal by the sampling signal and generates a synchronization signal according to a sampling result. The match circuit generates a composite synchronization signal by a virtual signal and the synchronization signal, and captures a plurality of row data from the return-to-zero signal according to the composite synchronization signal.

Abstract: A data capture device including a signal processing unit, a frequency locked circuit and a match circuit is provided. The signal processing unit converts a radio frequency signal to a return-to-zero signal. The frequency locked circuit estimates a minimum interval length by the return-to-zero signal in a plurality of detecting periods, and generates an enable signal according to the minimum interval length and the return-to-zero signal. The frequency locked circuit determines whether to calibrate the enable signal according to a distribution of a plurality of enable pulses in the enable signal to generate a sampling signal. The match circuit samples the return-to-zero signal by the sampling signal and generates a synchronization signal according to a sampling result. The match circuit generates a composite synchronization signal by a virtual signal and the synchronization signal, and captures a plurality of row data from the return-to-zero signal according to the composite synchronization signal.

Abstract: An apparatus for detecting burst cutting areas on optical discs includes an optical pickup head, a front-end processing unit, a sync pattern detector, a channel clock recovery device, and a data demodulator. The front-end processing unit generates a BCA signal in response to a radio frequency signal. The sync pattern detector counts the BCA signal according to a reference clock, detects a sync pattern of the BCA signal and outputs a channel bit length counting value. The channel clock recovery device generates a channel clock according to the reference clock and the channel bit length counting value. The data demodulator transfers the BCA signal into a BCA data according to the channel clock. The sync pattern detector continuously counts the BCA signal and continuously outputs a plurality of counting values, so that the sync pattern of the BCA signal can be determined according to at least three sequential counting values.

Abstract: An erasure information marking method for a burst cutting area (BCA) of a blu-ray disc (BD) is provided. The erasure information marking method includes obtaining at least four raw data recorded in the BCA; recognizing a record type of the BCA according to the four raw data; obtaining two duplicate copyright protection data, relating to the copyright protection of the BD, in the four raw data according to the record type of the BCA; and marking the erasure information of the BCA according to the difference between the two duplicate copyright protection data.

Abstract: An apparatus for detecting burst cutting areas on optical discs includes an optical pickup head, a front-end processing unit, a sync pattern detector, a channel clock recovery device, and a data demodulator. The front-end processing unit generates a BCA signal in response to a radio frequency signal. The sync pattern detector counts the BCA signal according to a reference clock, detects a sync pattern of the BCA signal and outputs a channel bit length counting value. The channel clock recovery device generates a channel clock according to the reference clock and the channel bit length counting value. The data demodulator transfers the BCA signal into a BCA data according to the channel clock. The sync pattern detector continuously counts the B CA signal and continuously outputs a plurality of counting values, so that the sync pattern of the BCA signal can be determined according to at least three sequential counting values.