Patents by Inventor Ping-Chieh Chiang

Ping-Chieh Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DRAM STRUCTURE WITH BURIED WORD LINES AND FABRICATION THEREOF, AND IC STRUCTURE AND FABRICATION THEREOF
    Publication number: 20140042548
    Abstract: A DRAM structure with buried word lines is described, including a semiconductor substrate, cell word lines buried in the substrate and separated from the same by a first gate dielectric layer, and isolation word lines buried in the substrate and separated from the same by a second gate dielectric layer. The top surfaces of the cell word lines and those of the isolation word lines are lower than the top surface of the substrate. The bottom surfaces of the isolation word lines are lower than those of the cell word lines.
    Type: Application
    Filed: October 7, 2013
    Publication date: February 13, 2014
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Hao-Chieh Liu, Lars Heineck, Ping-Chieh Chiang
  • DRAM STRUCTURE WITH BURIED WORD LINES AND FABRICATION THEREOF, AND IC STRUCTURE AND FABRICATION THEREOF
    Publication number: 20120292716
    Abstract: A DRAM structure with buried word lines is described, including a semiconductor substrate, cell word lines buried in the substrate and separated from the same by a first gate dielectric layer, and isolation word lines buried in the substrate and separated from the same by a second gate dielectric layer. The top surfaces of the cell word lines and those of the isolation word lines are lower than the top surface of the substrate. The bottom surfaces of the isolation word lines are lower than those of the cell word lines.
    Type: Application
    Filed: May 17, 2011
    Publication date: November 22, 2012
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Hao-Chieh Liu, Lars Heineck, Ping-Chieh Chiang