Patents by Inventor Ping-Chieh Huang

Ping-Chieh Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240119283
    Abstract: A method of performing automatic tuning on a deep learning model includes: utilizing an instruction-based learned cost model to estimate a first type of operational performance metrics based on a tuned configuration of layer fusion and tensor tiling; utilizing statistical data gathered during a compilation process of the deep learning model to determine a second type of operational performance metrics based on the tuned configuration of layer fusion and tensor tiling; performing an auto-tuning process to obtain a plurality of optimal configurations based on the first type of operational performance metrics and the second type of operational performance metrics; and configure the deep learning model according to one of the plurality of optimal configurations.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 11, 2024
    Applicant: MEDIATEK INC.
    Inventors: Jui-Yang Hsu, Cheng-Sheng Chan, Jen-Chieh Tsai, Huai-Ting Li, Bo-Yu Kuo, Yen-Hao Chen, Kai-Ling Huang, Ping-Yuan Tseng, Tao Tu, Sheng-Je Hung
  • Publication number: 20240087644
    Abstract: A forming operation of resistive memory device is provided. The operation includes: applying a pre-forming gate voltage and a pre-forming bit line voltage to a target memory cell; performing a dense switching forming operation, wherein the dense switching forming operation includes alternately performing dense set operations and dense reset operations on the target memory cell, wherein the dense set operation includes applying a dense switching gate voltage and a dense set bit line voltage; and performing a normal set operation on the target memory cell, wherein the normal set operation includes applying a normal set gate voltage and a normal set bit line voltage to the target memory cell, the normal set gate voltage is greater than the pre-forming gate voltage and the dense switching gate voltage, and the normal set bit line voltage is less than the pre-forming bit line voltage and the dense set bit line voltage.
    Type: Application
    Filed: August 29, 2023
    Publication date: March 14, 2024
    Applicant: Winbond Electronics Corp.
    Inventors: I-Hsien Tseng, Lung-Chi Cheng, Ju-Chieh Cheng, Jun-Yao Huang, Ping-Kun Wang
  • Publication number: 20220390509
    Abstract: A testing equipment is provided, in which at least one testing module is disposed on a machine, and the testing module includes a circuit board, a testing carrier disposed on the circuit board and carrying a target object, and a processor disposed on the circuit board and electrically connected to the testing carrier, such that the testing module can operate and process a target information of the target object by itself via the processor, without connecting to an external computer to operate and process the target information of the target object, so as to quickly obtain a detecting information of the target object.
    Type: Application
    Filed: May 16, 2022
    Publication date: December 8, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Li-Wei Lee, Yung-Ming Wang, Ping-Chieh Huang, Tien-Yao Hsu