Patents by Inventor Ping Chieh Wu
Ping Chieh Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160275232Abstract: The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by performing an initial data preparation process on an IC design including a graphical representation of a layout used to fabricate an integrated chip. The initial data preparation process is performed by using a data preparation element to generate a modified IC design having modified shapes that are modified forms of shapes within the IC design. One or more low-pattern-density areas of the modified IC design are identified using a local density checking element. One or more dummy shapes are added within the one or more low-pattern-density areas using a dummy shape insertion element. The one or more dummy shapes are separated from the modified shapes by a non-zero space.Type: ApplicationFiled: June 1, 2016Publication date: September 22, 2016Inventors: Hung-Chun Wang, Ming-Hui Chih, Ping-Chieh Wu, Chun-Hung Wu, Wen-Hao Liu, Cheng-Hsuan Huang, Cheng-Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
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Patent number: 9411924Abstract: The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by forming an integrated chip (IC) design that is a graphical representation of an integrated chip. One or more low-pattern-density areas of the IC design are identified having a pattern density that results in a processing failure. The low-pattern-density areas are a subset of the IC design. The pattern density is adjusted within the low-pattern-density area by adding one or more dummy shapes within the low-pattern-density areas. A data preparation process is then performed on the IC design to modify shapes of the one or more dummy shapes within the low-pattern-density areas. By introducing dummy shapes into a local area, rather than into an entire integrated chip design, the demands of the subsequent data preparation process are reduced.Type: GrantFiled: October 11, 2013Date of Patent: August 9, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Chun Wang, Ming-Hui Chih, Ping-Chieh Wu, Chun-Hung Wu, Wen-Hao Liu, Cheng-Hsuan Huang, Cheng-Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
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Publication number: 20160162627Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving an IC design layout, wherein the IC design layout includes multiple IC regions and each of the IC regions includes an initial IC pattern. The method further includes performing a correction process to a first IC region, thereby modifying the initial IC pattern in the first IC region to result in a first corrected IC pattern in the first IC region, wherein the correction process includes location effect correction. The method further includes replacing the initial IC pattern in a second IC region with the first corrected IC pattern.Type: ApplicationFiled: February 15, 2016Publication date: June 9, 2016Inventors: Hung-Chun Wang, Ching-Hsu Chang, Chun-Hung Wu, Cheng Kun Tsai, Feng-Ju Chang, Feng-Lung Lin, Ming-Hsuan WU, Ping-Chieh Wu, Ru-Gun Liu, Wen-Chun Huang, Wen-Hao Liu
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Patent number: 9280041Abstract: A method of photolithography including coupling a first aperture to a lithography system, then performing a first illumination process to form a first pattern on a layer of a substrate using the first aperture, thereafter coupling a second aperture to the lithography system, and performing a second illumination process to form a second pattern on the layer of the substrate using the second aperture. The first aperture includes a first pair and a second pair of radiation-transmitting regions. The second aperture includes a second plate having a third pair and a fourth pair of radiation-transmitting regions.Type: GrantFiled: March 8, 2013Date of Patent: March 8, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Cheng Wang, Hung Chang Hsieh, Shih-Che Wang, Ping Chieh Wu, Wen-Chun Huang, Ming-Chang Wen
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Patent number: 9262578Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving a design layout of an IC, wherein the design layout includes a plurality of non-overlapping IC regions and each of the IC regions includes a same initial IC pattern. The method further includes dividing the IC regions into a plurality of groups based on a location effect analysis such that all IC regions in a respective one of the groups are to have substantially same location effect. The method further includes performing a correction to one IC region in each of the groups using a correction model that includes location effect; and copying the corrected IC region to other IC regions in the respective group. The method further includes storing the corrected IC design layout in a tangible computer-readable medium for use by a further IC process stage.Type: GrantFiled: June 2, 2014Date of Patent: February 16, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chun Wang, Ching-Hsu Chang, Feng-Ju Chang, Chun-Hung Wu, Ping-Chieh Wu, Wen-Hao Liu, Ming-Hsuan Wu, Feng-Lung Lin, Cheng Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
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Patent number: 9189587Abstract: A method and computer program are provided for analyzing a set of layers within an integrated circuit design to determine a set of critical points for each layer within the set of layers. The critical points are based at least in part on manufacturer specific process parameters. The method includes assigning a critical point value to each of the critical points within each set of critical points, analyzing a path through the integrated circuit design across multiple integrated circuit design layers, and determining a sum of critical point values of each critical point along the path.Type: GrantFiled: October 3, 2013Date of Patent: November 17, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: I-Chang Shih, Jen-Chieh Lo, Tzu-Chin Lin, Ping-Chieh Wu, Ying-Chou Cheng, Chih-Ming Lai, Ru-Gun Liu
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Publication number: 20150310158Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving a design layout of an IC, wherein the design layout includes a plurality of non-overlapping IC regions and each of the IC regions includes a same initial IC pattern. The method further includes dividing the IC regions into a plurality of groups based on a location effect analysis such that all IC regions in a respective one of the groups are to have substantially same location effect. The method further includes performing a correction to one IC region in each of the groups using a correction model that includes location effect; and copying the corrected IC region to other IC regions in the respective group. The method further includes storing the corrected IC design layout in a tangible computer-readable medium for use by a further IC process stage.Type: ApplicationFiled: June 2, 2014Publication date: October 29, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chun Wang, Ching-Hsu Chang, Feng-Ju Chang, Chun-Hung Wu, Ping-Chieh Wu, Wen-Hao Liu, Ming-Hsuan Wu, Feng-Lung Lin, Cheng Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
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Patent number: 9165095Abstract: A method performed by a computer processing system includes receiving a design pattern for an integrated circuit, applying a function to the design pattern to generate a model contour, generating a plurality of Optical Proximity Correction (OPC) target points along the model contour, adjusting the design pattern to create an adjusted pattern, and performing a simulation on the adjusted pattern to create a simulated contour.Type: GrantFiled: November 15, 2013Date of Patent: October 20, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Hui Chih, Wen-Li Cheng, Yu-Po Tang, Ping-Chieh Wu, Chia-Ping Chiang, Yong-Cheng Lin, Wen-Chun Huang, Ru-Gun Liu
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Publication number: 20150143304Abstract: A method performed by a computer processing system includes receiving a design pattern for an integrated circuit, applying a function to the design pattern to generate a model contour, generating a plurality of Optical Proximity Correction (OPC) target points along the model contour, adjusting the design pattern to create an adjusted pattern, and performing a simulation on the adjusted pattern to create a simulated contour.Type: ApplicationFiled: November 15, 2013Publication date: May 21, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Hui Chih, Wen-Li Cheng, Yu-Po Tang, Ping-Chieh Wu, Chia-Ping Chiang, Yong-Cheng Lin, Wen-Chun Huang, Ru-Gun Liu
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Patent number: 9026955Abstract: The present disclosure relates to a method of integrated chip (IC) design pattern correction that reduces pattern correction cycle time by separately correcting main feature shapes and dummy shapes of the IC design, and an associated apparatus. In some embodiments, the method is performed by forming an IC design having a plurality of main feature shapes. A plurality of dummy shapes are added to the IC design to improve a process window of the IC design. The plurality of main feature shapes are corrected using a first pattern correction process. One or more of the plurality of dummy shapes are subsequently corrected using a second pattern correction process separate from the first pattern correction process. By separately correcting dummy shapes and main feature shapes, the dummy shapes can be subjected to a different pattern correction process having lower time/resource demands, thereby reducing the pattern correction cycle time.Type: GrantFiled: October 11, 2013Date of Patent: May 5, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hung-Chun Wang, Ming-Hui Chih, Ping-Chieh Wu, Chun-Hung Wu, Feng-Ju Chang, Cheng-Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
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Publication number: 20150106773Abstract: The present disclosure relates to a method of integrated chip (IC) design pattern correction that reduces pattern correction cycle time by separately correcting main feature shapes and dummy shapes of the IC design, and an associated apparatus. In some embodiments, the method is performed by forming an IC design having a plurality of main feature shapes. A plurality of dummy shapes are added to the IC design to improve a process window of the IC design. The plurality of main feature shapes are corrected using a first pattern correction process. One or more of the plurality of dummy shapes are subsequently corrected using a second pattern correction process separate from the first pattern correction process. By separately correcting dummy shapes and main feature shapes, the dummy shapes can be subjected to a different pattern correction process having lower time/resource demands, thereby reducing the pattern correction cycle time.Type: ApplicationFiled: October 11, 2013Publication date: April 16, 2015Inventors: Hung-Chun Wang, Ming-Hui Chih, Ping-Chieh Wu, Chun-Hung Wu, Feng-Ju Chang, Cheng-Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
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Publication number: 20150106779Abstract: The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by forming an integrated chip (IC) design that is a graphical representation of an integrated chip. One or more low-pattern-density areas of the IC design are identified having a pattern density that results in a processing failure. The low-pattern-density areas are a subset of the IC design. The pattern density is adjusted within the low-pattern-density area by adding one or more dummy shapes within the low-pattern-density areas. A data preparation process is then performed on the IC design to modify shapes of the one or more dummy shapes within the low-pattern-density areas. By introducing dummy shapes into a local area, rather than into an entire integrated chip design, the demands of the subsequent data preparation process are reduced.Type: ApplicationFiled: October 11, 2013Publication date: April 16, 2015Inventors: Hung-Chun Wang, Ming-Hui Chih, Ping-Chieh Wu, Chun-Hung Wu, Wen-Hao Liu, Cheng-Hsuan Huang, Cheng-Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
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Publication number: 20150100927Abstract: A method and computer program are provided for analyzing a set of layers within an integrated circuit design to determine a set of critical points for each layer within the set of layers. The critical points are based at least in part on manufacturer specific process parameters. The method includes assigning a critical point value to each of the critical points within each set of critical points, analyzing a path through the integrated circuit design across multiple integrated circuit design layers, and determining a sum of critical point values of each critical point along the path.Type: ApplicationFiled: October 3, 2013Publication date: April 9, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Chang Shih, Jen-Chieh Lo, Tzu-Chin Lin, Ping-Chieh Wu, Ying-Chou Cheng, Chih-Ming Lai, Ru-Gun Liu
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Patent number: 8954899Abstract: The present disclosure describes a method of calibrating a contour. The method includes designing an anchor pattern, printing the anchor pattern on a substrate, collecting scanning electron microscope (SEM) data of the printed anchor pattern on the substrate, wherein the SEM data includes a SEM image of the printed anchor pattern on the substrate, converting the SEM image of the printed anchor pattern on the substrate into a SEM contour of the printed anchor pattern, analyzing the SEM contour of the printed anchor pattern, and aligning the SEM contour of the anchor pattern to form the calibrated SEM contour.Type: GrantFiled: October 4, 2012Date of Patent: February 10, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ping-Chieh Wu, Tzu-Chin Lin, Hung-Ting Lu, Wen-Chun Huang, Ru-Gun Liu
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Publication number: 20140101624Abstract: The present disclosure describes a method of calibrating a contour. The method includes designing an anchor pattern, printing the anchor pattern on a substrate, collecting scanning electron microscope (SEM) data of the printed anchor pattern on the substrate, wherein the SEM data includes a SEM image of the printed anchor pattern on the substrate, converting the SEM image of the printed anchor pattern on the substrate into a SEM contour of the printed anchor pattern, analyzing the SEM contour of the printed anchor pattern, and aligning the SEM contour of the anchor pattern to form the calibrated SEM contour.Type: ApplicationFiled: October 4, 2012Publication date: April 10, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ping-Chieh Wu, Tzu-Chin Lin, Hung-Ting Lu, Wen-Chun Huang, Ru-Gun Liu
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Patent number: 8681326Abstract: The present disclosure is directed generally to a method and apparatus for monitoring mask process impact on lithography performance. A method including receiving a physical wafer pattern according to a mask, extracting a mask contour from the mask, and extracting a deconvolution pattern based on the mask contour. A lithography process is simulated to create a virtual wafer pattern based on the deconvolution pattern. The virtual wafer pattern is then compared to the physical wafer pattern.Type: GrantFiled: June 28, 2013Date of Patent: March 25, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ping-Chieh Wu, Chien-Hsun Chen, Ru-Gun Liu, Wen-Chun Huang, Chih-Ming Lai, Boren Luo
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Publication number: 20130290912Abstract: The present disclosure is directed generally to a method and apparatus for monitoring mask process impact on lithography performance. A method including receiving a physical wafer pattern according to a mask, extracting a mask contour from the mask, and extracting a deconvolution pattern based on the mask contour. A lithography process is simulated to create a virtual wafer pattern based on the deconvolution pattern. The virtual wafer pattern is then compared to the physical wafer pattern.Type: ApplicationFiled: June 28, 2013Publication date: October 31, 2013Inventors: Ping-Chieh Wu, Chien-Hsun Chen, Ru-Gun Liu, Wien-Chun Huang, Chih-Ming Lai, Boren Luo
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Patent number: 8477299Abstract: The present disclosure is directed generally to a method and apparatus for monitoring mask process impact on lithography performance. A method including receiving a physical wafer pattern according to a mask, extracting a mask contour from the mask, and extracting a deconvolution pattern based on the mask contour. A lithography process is simulated to create a virtual wafer pattern based on the deconvolution pattern. The virtual wafer pattern is then compared to the physical wafer pattern.Type: GrantFiled: April 1, 2010Date of Patent: July 2, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ping Chieh Wu, Chien-Hsun Chen, Ru-Gun Liu, Wen-Chun Huang, Chih-Ming Lai, Boren Luo
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Patent number: 8416393Abstract: Provided is a lithography system operation to include a first aperture or a second aperture. Each of the first and second apertures has two pairs of radiation-transmitting regions where one pair of radiation-transmitting regions are larger than a second pair. For an aperture, each pair of radiation-transmitting regions are on different diametrical axis. In an embodiment, one aperture is used for x-dipole illumination and the second aperture is used for y-dipole illumination.Type: GrantFiled: April 2, 2009Date of Patent: April 9, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Cheng Wang, Hung Chang Hsieh, Shih-Che Wang, Ping Chieh Wu, Wen-Chun Huang, Ming-Chang Wen
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Publication number: 20110243424Abstract: The present disclosure is directed generally to a method and apparatus for monitoring mask process impact on lithography performance. A method including receiving a physical wafer pattern according to a mask, extracting a mask contour from the mask, and extracting a deconvolution pattern based on the mask contour. A lithography process is simulated to create a virtual wafer pattern based on the deconvolution pattern. The virtual wafer pattern is then compared to the physical wafer pattern.Type: ApplicationFiled: April 1, 2010Publication date: October 6, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd. ("TSMC")Inventors: Ping Chieh Wu, Chien-Hsun Chen, Ru-Gun Liu, Wen-Chun Huang, Chih-Ming Lai, Boren Luo