Abstract: A method includes providing a substrate having a first region and a second region, forming a fin protruding from the first region, where the fin includes a first SiGe layer and a stack alternating Si layers and second SiGe layers disposed over the first SiGe layer and the first SiGe layer has a first concentration of Ge and each of the second SiGe layers has a second concentration of Ge that is greater than the first concentration, recessing the fin to form an S/D recess, recessing the first SiGe layer and the second SiGe layers exposed in the S/D recess, where the second SiGe layers are recessed more than the first SiGe layer, forming an S/D feature in the S/D recess, removing the recessed first SiGe layer and the second SiGe layers to form openings, and forming a metal gate structure over the fin and in the openings.

Abstract: Semiconductor devices having improved source/drain features and methods for fabricating such are disclosed herein. An exemplary device includes a semiconductor layer stack disposed over a mesa structure of a substrate. The device further includes a metal gate disposed over the semiconductor layer stack and an inner spacer disposed on the mesa structure of the substrate. The device further includes a first epitaxial source/drain feature and a second epitaxial source/drain feature where the semiconductor layer stack is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. The device further includes a void disposed between the inner spacer and the first epitaxial source/drain feature.

Abstract: SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a ? ratio of an SRAM cell.

Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided. The method includes: receiving a first write command from a host system; selecting a first physical erasing unit from at least one physical erasing unit available for writing and writing data corresponding to the first write command to the first physical erasing unit by using a single page programming mode or a multi-page programming mode when the number of physical erasing units available for writing is greater than a first threshold; and selecting a second physical erasing unit from the at least one physical erasing unit available for writing and writing data corresponding to the first write command into the second physical erasing unit by only using the single page programming mode when the number of physical erasing units available for writing is not greater than the first threshold.

Abstract: A data writing method, a memory control circuit unit, and a memory storage apparatus are provided. The method includes: receiving a write command from a host system; and determining whether to write a data corresponding to the write command into a first area or a second area according to a write amplification factor of the first area, where if it is determined to write the data into the second area, copying the written data to the first area after writing the data.

Abstract: A data writing method, a memory control circuit unit, and a memory storage apparatus are provided. The method includes: receiving a write command from a host system; and determining whether to write a data corresponding to the write command into a first area or a second area according to a write amplification factor of the first area, where if it is determined to write the data into the second area, copying the written data to the first area after writing the data.

Abstract: A data writing method, a memory storage device, and a memory control circuit unit are provided. The method includes: receiving a first data and writing the first data to at least one first physical programming unit of a first physical erasing unit; receiving a second data; temporarily storing the second data to a temporary storage area if a data length of the second data is less than a predefined value; receiving a third data; writing the third data to at least one second physical programming unit of the first physical erasing unit if a logical address storing the first data is consecutive with a logical address storing the third data; and moving the second data from the temporary storage area to at least one second physical programming unit of the first physical erasing unit if the logical address storing the first data is not consecutive with the logical address storing the third data.

Abstract: A memory management method, a memory storage device and a memory control circuit unit are provided. The method includes: storing first data to a first physical erasing unit and marking the first physical erasing unit as belonging to a first group, wherein the first data belongs to a first type; storing second data to a second physical erasing unit and marking the second physical erasing unit as belonging to a second group, wherein the second data belongs to a second type which is different from the first type; selecting a third physical erasing unit as an active physical erasing unit and marking the third physical erasing unit as belonging to the first group; when a data moving operation is performed, moving valid data of the first physical erasing unit to the third physical erasing unit according to a first parameter of the first physical erasing unit.

Abstract: A data writing method, a memory storage device, and a memory control circuit unit are provided. The method includes: receiving a first data and writing the first data to at least one first physical programming unit of a first physical erasing unit; receiving a second data; temporarily storing the second data to a temporary storage area if a data length of the second data is less than a predefined value; receiving a third data; writing the third data to at least one second physical programming unit of the first physical erasing unit if a logical address storing the first data is consecutive with a logical address storing the third data; and moving the second data from the temporary storage area to at least one second physical programming unit of the first physical erasing unit if the logical address storing the first data is not consecutive with the logical address storing the third data.

Abstract: A data writing method, a memory control circuit unit, and a memory storage device are provided.

Abstract: A memory management method, a memory storage device and a memory control circuit unit are provided. The method includes: storing first data to a first physical erasing unit and marking the first physical erasing unit as belonging to a first group, wherein the first data belongs to a first type; storing second data to a second physical erasing unit and marking the second physical erasing unit as belonging to a second group, wherein the second data belongs to a second type which is different from the first type; selecting a third physical erasing unit as an active physical erasing unit and marking the third physical erasing unit as belonging to the first group; when a data moving operation is performed, moving valid data of the first physical erasing unit to the third physical erasing unit according to a first parameter of the first physical erasing unit.

Abstract: The invention provides a memory management method, a memory storage device, and a memory control circuit unit. The method includes: recording an error bit number of each upper physical programming unit and an error bit number of each lower physical programming unit of each of the physical erasing units; determining whether a first physical erasing unit is a bad physical erasing unit according to distributions of the error bit numbers of the upper physical programming units and the lower physical programming units of the first physical erasing unit of the physical erasing units; and performing a data transfer operation on data in the first physical erasing unit if the first physical erasing unit is determined as the bad physical erasing unit.