Abstract: A circuit for data processing is provided. The circuit comprises a dual-mode adder, a max finder circuit, a zone detector circuit and an alignment circuit. The dual-mode adder generates products between first exponents of first floating point numbers and second exponents of second floating point numbers. The max finder circuit finds a maximum among first portions of the products. The zone detector circuit classify the first portions into zones by comparing the first portions and the maximum. The alignment circuit align first mantissas of the first floating point numbers according to the zones and second portions of the products to generate aligned mantissas for a floating point number operation.

Abstract: In this disclosure, a storage circuit is provided. The storage circuit includes a gain-cell, a self-refresh unit, and a latch circuit. The gain-cell is configured to store first data in a gate of a storage transistor. The self-refresh unit is configured to read the first data from the gain-cell and write the first data back to the gain-cell. The latch circuit is configured to read the first data from the self-refresh unit and latch the first data.

Abstract: A method for forming a semiconductor device structure includes forming nanostructures over a substrate. The method also includes forming a gate structure wrapped around the nanostructures. The method also includes forming source/drain epitaxial structures over opposite sides of the nanostructures. The method also includes forming an interlayer dielectric structure over the source/drain epitaxial structures. The method also includes etching the interlayer dielectric structure to form an opening exposing the source/drain epitaxial structures. The method also includes depositing a first spacer layer over sidewalls of the interlayer dielectric structure in the opening. The method also includes forming a silicide structure over the source/drain epitaxial structures. The method also includes forming a bottom contact structure over the silicide structure. The method also includes depositing a second spacer layer over the first spacer layer.

Abstract: Memory systems and operating method of a memory system are provided. The memory system utilized for performing a computing-in-memory (CiM) operation comprises a memory array and a processing circuit. The memory array comprises a plurality of memory cells. The processing circuit is coupled to the memory array and comprises a programming circuit and a control circuit. The programming circuit is coupled to the memory array and configured to perform a write operation for programming electrical characteristics of the memory cells. The control circuit is coupled to the programming circuit and configured to: receive a plurality of weight data corresponding to a plurality of weight values; and control the write operation performed by the programming circuit, so the electrical characteristics of the memory cells are programmed following a sequential order of the weight values.

Abstract: A circuit includes local computing cells. Each of the local computing cells can provide, in response to identifying that the input data elements and weight data elements are in a first data type, a first sum including (i) a first product of a first input data element and a first weight data element; and (ii) a second product of a second input data element and a second weight data element. Each of the local computing cells can provide, in response to identifying that the input data elements and weight data elements are in a second data type, (i) a second sum of a first portion of a third input data element and a first portion of a third weight data element; and (ii) a third product of a second portion of the third input data element and a second portion of the third weight data element.

Abstract: A method for forming a semiconductor device structure includes forming nanostructures over a substrate. The method also includes forming a gate structure wrapped around the nanostructures. The method also includes forming source/drain epitaxial structures over opposite sides of the nanostructures. The method also includes forming a first interlayer dielectric structure over the source/drain epitaxial structures. The method also includes removing the first interlayer dielectric structure. The method also includes forming a recess in the source/drain epitaxial structures. The method also includes forming a silicide structure in the recess. The method also includes forming a second interlayer dielectric structure over the silicide structure.

Abstract: Memory systems and operating method of a memory system are provided. The memory system utilized for performing a computing-in-memory (CiM) operation comprises a memory array and a processing circuit. The memory array comprises a plurality of memory cells. The processing circuit is coupled to the memory array and comprises a programming circuit and a control circuit. The programming circuit is coupled to the memory array and configured to perform a write operation for programming electrical characteristics of the memory cells. The control circuit is coupled to the programming circuit and configured to: receive a plurality of weight data corresponding to a plurality of weight values; and control the write operation performed by the programming circuit, so the electrical characteristics of the memory cells are programmed following a sequential order of the weight values.

Abstract: Memory systems and operating method of a memory system are provided. The memory system utilized for performing a computing-in-memory (CiM) operation comprises a memory array and a processing circuit. The memory array comprises a plurality of memory cells. The processing circuit is coupled to the memory array and comprises a programming circuit and a control circuit. The programming circuit is coupled to the memory array and configured to perform a write operation for programming electrical characteristics of the memory cells. The control circuit is coupled to the programming circuit and configured to: receive a plurality of weight data corresponding to a plurality of weight values; and control the write operation performed by the programming circuit, so the electrical characteristics of the memory cells are programmed following a sequential order of the weight values.

Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a source/drain region disposed over a substrate, a first interlayer dielectric layer surrounding a first portion of the source/drain region, a second interlayer dielectric layer distinct from the first interlayer dielectric layer surrounding a second portion of the source/drain region, a silicide layer disposed on the source/drain region, and a conductive contact disposed over the source/drain region. The conductive contact is disposed in the second interlayer dielectric layer.

Abstract: A hybrid structure for computing-in-memory applications includes a memory cell and a digital-analog-hybrid local computing cell. The memory cell stores a weight. The digital-analog-hybrid local computing cell has a plurality of input lines, a digital output line and an analog output line. The input lines are configured to transmit a plurality of multi-bit input values. The digital-analog-hybrid local computing cell includes a digital local computing cell and a voltage local computing cell. The digital local computing cell receives the weight and is configured to generate a digital output value on the digital output line according to a higher bit of the multi-bit input values multiplied by the weight. The voltage local computing cell receives the weight and is configured to generate an analog output value on the analog output line according to a lower bit of the multi-bit input values multiplied by the weight.

Abstract: A floating point pre-alignment structure for computing-in-memory applications includes a time domain exponent computing block and an input mantissa pre-align block. The time domain exponent computing block is configured to compute a plurality of original input exponents and a plurality of original weight exponents to generate a plurality of flags. Each of the flags is determined by adding one of the original input exponents and one of the original weight exponents. The input mantissa pre-align block is configured to receive a plurality of original input mantissas and shift the original input mantissas according to the flags to generate a plurality of weighted input mantissas, and sparsity of the weighted input mantissas is greater than sparsity of the original input mantissas. Each of the flags has a negative correlation with a sum of the one of the original input exponents and the one of the original weight exponents.

Abstract: A memory unit with time domain edge delay accumulation for computing-in-memory applications is controlled by a first word line and a second word line. The memory unit includes at least one memory cell, at least one edge-delay cell multiplexor and at least one edge-delay cell. The at least one edge-delay cell includes a weight reader and a driver. The weight reader is configured to receive a weight and a multi-bit analog input voltage and generate a multi-bit voltage according to the weight and the multi-bit analog input voltage. The driver is connected to the weight reader and configured to receive an edge-input signal. The driver is configured to generate an edge-output signal having a delay time according to the edge-input signal and the multi-bit voltage. The delay time of the edge-output signal is positively correlated with the multi-bit analog input voltage multiplied by the weight.

Abstract: Memory systems and operating method of a memory system are provided. The memory system utilized for performing a computing-in-memory (CiM) operation comprises a memory array and a processing circuit. The memory array comprises a plurality of memory cells. The processing circuit is coupled to the memory array and comprises a programming circuit and a control circuit. The programming circuit is coupled to the memory array and configured to perform a write operation for programming electrical characteristics of the memory cells. The control circuit is coupled to the programming circuit and configured to: receive a plurality of weight data corresponding to a plurality of weight values; and control the write operation performed by the programming circuit, so the electrical characteristics of the memory cells are programmed following a sequential order of the weight values.

Abstract: Embodiments include monitoring a partial sum of a multiply accumulate calculation for certain conditions. When the certain conditions are met, a reduced read energy is used to read out memory contents instead of the regular read energy used. The reduced read energy may be obtained by reducing a pre-charge voltage, withholding a pre-charge voltage or providing a ground signal, and/or by reducing voltage hold times (i.e., reducing the time a pre-charge voltage is provided and/or discharged).

Abstract: A dynamic differential-reference time-to-digital converter for computing-in-memory applications is controlled by a bias reference and a predetermined setting parameter, and includes a configurable main-reference selector and a plurality of time-to-digital converters. The configurable main-reference selector is configured to receive a plurality of edge-output signals, select one of the edge-output signals as a main reference and select others of the edge-output signals as a plurality of edge selected signals according to the predetermined setting parameter. One of the time-to-digital converters is configured to compare the bias reference with the main reference to output a bias multiplication-and-accumulation value, and others of the time-to-digital converters are configured to compare the main reference with the edge selected signals to output a plurality of differential multiplication-and-accumulation values.

Abstract: A memory unit with time domain edge delay accumulation for computing-in-memory applications is controlled by a first word line and a second word line. The memory unit includes at least one memory cell, at least one edge-delay cell multiplexor and at least one edge-delay cell. The at least one edge-delay cell includes a weight reader and a driver. The weight reader is configured to receive a weight and a multi-bit analog input voltage and generate a multi-bit voltage according to the weight and the multi-bit analog input voltage. The driver is connected to the weight reader and configured to receive an edge-input signal. The driver is configured to generate an edge-output signal having a delay time according to the edge-input signal and the multi-bit voltage. The delay time of the edge-output signal is positively correlated with the multi-bit analog input voltage multiplied by the weight.

Abstract: A memory structure with input-aware maximum multiply-and-accumulate value zone prediction for computing-in-memory applications includes a memory array, an input-aware zone prediction circuit and an analog-to-digital converter. An input-aware maximum partial multiply-and-accumulate value voltage generator is configured to generate a maximum partial multiply-and-accumulate value according to at least one input value. A prediction-aware global reference voltage generator is configured to generate a plurality of global reference voltages, a maximum reference voltage and a selected minimum reference voltage. A maximum partial multiply-and-accumulate value zone detector is configured to generate a zone switch signal by comparing the maximum partial multiply-and-accumulate value and the global reference voltages.

Abstract: The present invention provides a method for manufacturing an epitaxial film and the epitaxial film thereof. The method comprises the steps of: providing a first single crystal substrate and forming a sacrificial layer and a first epitaxial film on the first single crystal substrate; removing the sacrificial layer in order to separate the first epitaxial film from the first single crystal substrate; shifting the first epitaxial film to a second single crystal substrate so as to let the first epitaxial film cover on a partial surface of the second single crystal substrate, wherein the first epitaxial film and the second single crystal substrate are two different crystallographic plane orientations in absolute coordinates; and forming a second epitaxial film on the first epitaxial film and the second single crystal substrate, so as to let the second epitaxial film has at least two crystallographic plane orientations.