Patents by Inventor Ping-chun Yeh
Ping-chun Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220289564Abstract: A method includes forming a front-end-of-the-line (FEOL) element over a substrate; forming a back-end-of-the-line (BEOL) element over the FEOL element; forming an interconnection structure over the substrate; forming a conductive shielding layer electrically connected to the interconnection structure and vertically overlapping the FEOL element and the BEOL element, wherein the conductive shielding layer is grounded to the substrate through the interconnection structure; and forming a dielectric layer covering the conductive shielding layer.Type: ApplicationFiled: May 27, 2022Publication date: September 15, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ping-Chun YEH, Lien-Yao TSAI, Shao-Chi YU
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Patent number: 11345591Abstract: A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate. an orthogonal projection of the conductive shielding layer on the semiconductor substrate does not overlap with an orthogonal projection of the FEOL element on the semiconductor substrate.Type: GrantFiled: December 16, 2019Date of Patent: May 31, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ping-Chun Yeh, Lien-Yao Tsai, Shao-Chi Yu
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Publication number: 20200115223Abstract: A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate. an orthogonal projection of the conductive shielding layer on the semiconductor substrate does not overlap with an orthogonal projection of the FEOL element on the semiconductor substrate.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ping-Chun YEH, Lien-Yao TSAI, Shao-Chi YU
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Patent number: 10508028Abstract: A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate.Type: GrantFiled: December 4, 2018Date of Patent: December 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ping-Chun Yeh, Lien-Yao Tsai, Shao-Chi Yu
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Publication number: 20190112184Abstract: A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate.Type: ApplicationFiled: December 4, 2018Publication date: April 18, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ping-Chun YEH, Lien-Yao TSAI, Shao-Chi YU
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Patent number: 10155660Abstract: A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate.Type: GrantFiled: January 28, 2015Date of Patent: December 18, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ping Chun Yeh, Lien-Yao Tsai, Shao-Chi Yu
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Publication number: 20160214855Abstract: A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate.Type: ApplicationFiled: January 28, 2015Publication date: July 28, 2016Inventors: Ping Chun YEH, Lien-Yao TSAI, Shao-Chi YU
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Patent number: 8338906Abstract: An integrated circuit structure has a metal silicide layer formed on an n-type well region, a p-type guard ring formed on the n-type well region and encircling the metal silicide layer. The outer portion of the metal silicide layer extends to overlap the inner edge of the guard ring, and a Schottky barrier is formed at the junction of the internal portion of the metal silicide layer and the well region. A conductive contact is in contact with the internal portion and the outer portion of the metal silicide layer.Type: GrantFiled: December 8, 2008Date of Patent: December 25, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ping-Chun Yeh, Der-Chyang Yeh, Ruey-Hsin Liu, Mingo Liu
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Patent number: 8334579Abstract: An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The integrated circuit device includes a substrate, a diffusion source, and a lightly doped diffusion region in contact with a conductive layer. A junction of the lightly doped diffusion region with the conductive layer forms a Schottky region. An annealing process is performed to form the lightly doped diffusion region. The annealing process causes dopants from the diffusion source (for example, an n-well disposed in the substrate) of the integrated circuit device to diffuse into a region of the substrate, thereby forming the lightly doped diffusion region.Type: GrantFiled: October 7, 2010Date of Patent: December 18, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ping Chun Yeh, Der-Chyang Yeh, Chih-Ping Chao
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Publication number: 20120086099Abstract: An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The integrated circuit device includes a substrate, a diffusion source, and a lightly doped diffusion region in contact with a conductive layer. A junction of the lightly doped diffusion region with the conductive layer forms a Schottky region. An annealing process is performed to form the lightly doped diffusion region. The annealing process causes dopants from the diffusion source (for example, an n-well disposed in the substrate) of the integrated circuit device to diffuse into a region of the substrate, thereby forming the lightly doped diffusion region.Type: ApplicationFiled: October 7, 2010Publication date: April 12, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ping Chun Yeh, Der-Chyang Yeh, Chih-Ping Chao
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Publication number: 20090283841Abstract: An integrated circuit structure has a metal silicide layer formed on an n-type well region, a p-type guard ring formed on the n-type well region and encircling the metal silicide layer. The outer portion of the metal silicide layer extends to overlap the inner edge of the guard ring, and a Schottky barrier is formed at the junction of the internal portion of the metal silicide layer and the well region. A conductive contact is in contact with the internal portion and the outer portion of the metal silicide layer.Type: ApplicationFiled: December 8, 2008Publication date: November 19, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ping-Chun Yeh, Der-Chyang Yeh, Ruey-Hsin Liu, Mingo Liu
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Patent number: 6859103Abstract: A bias circuit is provided for improving linearity of a radio frequency power amplifier. The bias circuit includes a bias transistor having a collector, an emitter, and a base. The collector is connected to a DC voltage source, the emitter is connected to a radio frequency transistor, and the base is connected to a bias voltage source. A capacitor and an inductor are connected in series and are coupled either between the emitter of the bias transistor and ground or between the base of the bias transistor and ground, thereby constructing an LC series-connected resonator circuit. The LC series-connected resonator circuit directly conducts the part of the radio frequency input signal, which is coupled back to the bias transistor, into the ground, thereby improving linearity of the radio frequency power amplifier. Preferably, the LC series-connected resonator circuit is designed to have a resonant frequency, which is equal to a frequency of a second harmonic component of the radio frequency input signal.Type: GrantFiled: August 22, 2003Date of Patent: February 22, 2005Assignee: Delta Electronics, Inc.Inventor: Ping-chun Yeh
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Publication number: 20040251966Abstract: A bias circuit is provided for improving linearity of a radio frequency power amplifier. The bias circuit includes a bias transistor having a collector, an emitter, and a base. The collector is connected to a DC voltage source, the emitter is connected to a radio frequency transistor, and the base is connected to a bias voltage source. A capacitor and an inductor are connected in series and are coupled either between the emitter of the bias transistor and ground or between the base of the bias transistor and ground, thereby constructing an LC series-connected resonator circuit. The LC series-connected resonator circuit directly conducts the part of the radio frequency input signal, which is coupled back to the bias transistor, into the ground, thereby improving linearity of the radio frequency power amplifier. Preferably, the LC series-connected resonator circuit is designed to have a resonant frequency, which is equal to a frequency of a second harmonic component of the radio frequency input signal.Type: ApplicationFiled: August 22, 2003Publication date: December 16, 2004Inventor: Ping-chun Yeh