Abstract: An image sensor structure and a method for forming the same are provided. The image sensor structure includes a first substrate including a first radiation sensing region and a first interconnect structure formed over a front side of the first substrate. The image sensor structure further includes a second substrate including a second radiation sensing region and a second interconnect structure formed over a front side of the second substrate. In addition, the first interconnect structure is bonded with the second interconnect structure.

Abstract: An image sensor structure and a method for forming the same are provided. The image sensor structure includes a first substrate including a first radiation sensing region and a first interconnect structure formed over a front side of the first substrate. The image sensor structure further includes a second substrate including a second radiation sensing region and a second interconnect structure formed over a front side of the second substrate. In addition, the first interconnect structure is bonded with the second interconnect structure.

Abstract: An integrated circuit device includes a transfer-gate transistor, and a photo diode connected to a source/drain region of the transfer-gate transistor. An electrical fuse is electrically coupled to a gate of the transfer-gate transistor. A diode is electrically coupled to the electrical fuse.

Abstract: An integrated circuit device includes a transfer-gate transistor, and a photo diode connected to a source/drain region of the transfer-gate transistor. An electrical fuse is electrically coupled to a gate of the transfer-gate transistor. A diode is electrically coupled to the electrical fuse.

Abstract: An integrated circuit device includes a transfer-gate transistor, and a photo diode connected to a source/drain region of the transfer-gate transistor. An electrical fuse is electrically coupled to a gate of the transfer-gate transistor. A diode is electrically coupled to the electrical fuse.

Abstract: An integrated circuit device includes a transfer-gate transistor, and a photo diode connected to a source/drain region of the transfer-gate transistor. An electrical fuse is electrically coupled to a gate of the transfer-gate transistor. A diode is electrically coupled to the electrical fuse.

Abstract: A representative electrostatic discharge (ESD) protection circuit includes a silicon-controlled rectifier (SCR) that is electrically coupled to the output of a power amplifier; an ESD detection circuit that triggers the SCR responsive to detect an electrostatic discharge on an ESD bus; and an ESD clamp circuit that is coupled to the first voltage line.

Abstract: An electrostatic discharge (ESD) circuit, adaptive to a radio frequency (RF) device, which includes a RF circuit coupled between a VDD power rail and a VSS power rail and having a RF I/O pad, includes an ESD clamp circuit coupled between a VDD power rail node and the VSS power rail node and a LC-tank structure coupled between the VDD power rail node and the VSS power rail node and to the RF I/O pad. The LC-tank structure includes a first ESD block between the VDD power rail node and the RF I/O pad, and a second ESD block between the VSS power rail node and the RF I/O pad. At least one of the first and second ESD blocks includes a pair of diodes coupled in parallel with each other and an inductor coupled in series with one of the pair of diodes.

Abstract: A representative electrostatic discharge (ESD) protection circuit includes a silicon-controlled rectifier (SCR) that is electrically coupled to the output of a power amplifier; an ESD detection circuit that triggers the SCR responsive to detect an electrostatic discharge on an ESD bus; and an ESD clamp circuit that is coupled to the first voltage line.

Abstract: An electrostatic discharge (ESD) circuit, adaptive to a radio frequency (RF) device, which includes a RF circuit coupled between a VDD power rail and a VSS power rail and having a RF I/O pad, includes an ESD clamp circuit coupled between a VDD power rail node and the VSS power rail node and a LC-tank structure coupled between the VDD power rail node and the VSS power rail node and to the RF I/O pad. The LC-tank structure includes a first ESD block between the VDD power rail node and the RF I/O pad, and a second ESD block between the VSS power rail node and the RF I/O pad. At least one of the first and second ESD blocks includes a pair of diodes coupled in parallel with each other and an inductor coupled in series with one of the pair of diodes.

Abstract: A semiconductor structure includes a refractory metal silicide layer; a silicon-rich refractory metal silicide layer on the refractory metal silicide layer; and a metal-rich refractory metal silicide layer on the silicon-rich refractory metal silicide layer. The refractory metal silicide layer, the silicon-rich refractory metal silicide layer and the metal-rich refractory metal silicide layer include same refractory metals. The semiconductor structure forms a portion of a gate electrode of a metal-oxide-semiconductor device.

Abstract: A semiconductor structure includes a refractory metal silicide layer; a silicon-rich refractory metal silicide layer on the refractory metal silicide layer; and a metal-rich refractory metal silicide layer on the silicon-rich refractory metal silicide layer. The refractory metal silicide layer, the silicon-rich refractory metal silicide layer and the metal-rich refractory metal silicide layer include same refractory metals. The semiconductor structure forms a portion of a gate electrode of a metal-oxide-semiconductor device.