Patents by Inventor Ping-Feng Yang
Ping-Feng Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210327731Abstract: A mass transfer method, a mass transfer device and a buffer carrier are provided. The mass transfer method includes: (a) providing a plurality of electronic components disposed on a source carrier; (b) providing a buffer carrier including a plurality of adjusting cavities; and (c) transferring the electronic components from the source carrier to the buffer carrier, wherein the electronic components are placed in the adjusting cavities of the buffer carrier to adjust positions of the electronic components from shifted positions to correct positions.Type: ApplicationFiled: April 15, 2020Publication date: October 21, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chih-Wen CHANG, Yu-Ho HSU, Tai-Yuan HUANG, Ping-Feng YANG, Fu-Ting CHANG, Chin-Feng WANG
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Patent number: 11075186Abstract: A semiconductor package includes a substrate, a semiconductor chip and a heat dissipation structure. The semiconductor chip includes a first surface, a second surface opposite to the first surface, and at least one chip pad disposed adjacent to the first surface. The chip pad is electrically connected to the substrate. The heat dissipation structure is disposed adjacent to the second surface of the semiconductor chip and a portion of the substrate. An area of the heat dissipation structure is greater than an area of the semiconductor chip.Type: GrantFiled: February 9, 2017Date of Patent: July 27, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Ian Hu, Jia-Rung Ho, Jin-Feng Yang, Chih-Pin Hung, Ping-Feng Yang
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Patent number: 10818517Abstract: A method for manufacturing a semiconductor package structure includes providing a semiconductor chip, encapsulating the semiconductor chip via a package body, the package body having a first surface opposite to a second surface, and coating a first self-assembled monolayer (SAM) over the first surface and the second surface of the package body.Type: GrantFiled: February 25, 2019Date of Patent: October 27, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Huang Han Chen, Ping-Feng Yang
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Publication number: 20200273724Abstract: A method for manufacturing a semiconductor package structure includes providing a semiconductor chip, encapsulating the semiconductor chip via a package body, the package body having a first surface opposite to a second surface, and coating a first self-assembled monolayer (SAM) over the first surface and the second surface of the package body.Type: ApplicationFiled: February 25, 2019Publication date: August 27, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Huang Han CHEN, Ping-Feng YANG
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Patent number: 10658319Abstract: A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent to the surface of the semiconductor element and connected to the trace, and a pillar disposed on the bonding pad. The pillar includes a first end wall, a second end wall opposite the first end wall, a first side wall, and a second side wall opposite the first side wall. The first side wall and the second side wall connect the first end wall to the second end wall. One or both of the first side wall and the second side wall incline inwardly from the first end wall to the second end wall. The pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall.Type: GrantFiled: January 14, 2019Date of Patent: May 19, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chih-Pin Hung, Dao-Long Chen, Ying-Ta Chiu, Ping-Feng Yang
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Publication number: 20190214323Abstract: A semiconductor package includes a filler composition, wherein the filler composition includes particles each including both carbon and silica, wherein the filler composition is substantially devoid of alumina or silicon carbide, and the filler composition has a weight ratio of carbon to silica of at least greater than 1.0.Type: ApplicationFiled: March 14, 2019Publication date: July 11, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Ya-Yu HSIEH, Hong-Ping LIN, Dao-Long CHEN, Ping-Feng YANG, Meng-Kai SHIH
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Publication number: 20190148326Abstract: A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent to the surface of the semiconductor element and connected to the trace, and a pillar disposed on the bonding pad. The pillar includes a first end wall, a second end wall opposite the first end wall, a first side wall, and a second side wall opposite the first side wall. The first side wall and the second side wall connect the first end wall to the second end wall. One or both of the first side wall and the second side wall incline inwardly from the first end wall to the second end wall. The pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall.Type: ApplicationFiled: January 14, 2019Publication date: May 16, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chih-Pin HUNG, Dao-Long CHEN, Ying-Ta CHIU, Ping-Feng YANG
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Patent number: 10181448Abstract: A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent to the surface of the semiconductor element and connected to the trace, and a pillar disposed on the bonding pad. The pillar includes a first end wall, a second end wall opposite the first end wall, a first side wall, and a second side wall opposite the first side wall. The first side wall and the second side wall connect the first end wall to the second end wall. One or both of the first side wall and the second side wall incline inwardly from the first end wall to the second end wall. The pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall.Type: GrantFiled: March 22, 2016Date of Patent: January 15, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chih-Pin Hung, Dao-Long Chen, Ying-Ta Chiu, Ping-Feng Yang
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Publication number: 20180226320Abstract: A semiconductor package includes a substrate, a semiconductor chip and a heat dissipation structure. The semiconductor chip includes a first surface, a second surface opposite to the first surface, and at least one chip pad disposed adjacent to the first surface. The chip pad is electrically connected to the substrate. The heat dissipation structure is disposed adjacent to the second surface of the semiconductor chip and a portion of the substrate. An area of the heat dissipation structure is greater than an area of the semiconductor chip.Type: ApplicationFiled: February 9, 2017Publication date: August 9, 2018Inventors: Ian HU, Jia-Rung HO, Jin-Feng YANG, Chih-Pin HUNG, Ping-Feng YANG
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Patent number: 9960136Abstract: A semiconductor device includes a first circuit layer, a copper pillar disposed adjacent to the first circuit layer, a second circuit layer and a solder layer. The second circuit layer includes an electrical contact and a surface finish layer disposed on the electrical contact, wherein a material of the surface finish layer is a combination of at least two of nickel, gold, and palladium. The solder layer is disposed between the copper pillar and the surface finish layer. The solder layer includes a first intermetallic compound (IMC) and a second IMC, wherein the first IMC includes a combination of two or more of copper, nickel and tin, and the second IMC includes a combination of gold and tin, a combination of palladium and tin, or both.Type: GrantFiled: August 17, 2016Date of Patent: May 1, 2018Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yu-Hsiang Hsiao, Chiu-Wen Lee, Ping-Feng Yang, Kwang-Lung Lin
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Publication number: 20180114762Abstract: A semiconductor package structure includes a substrate, a semiconductor element, an encapsulant, an adhesion layer and a metal cap. The semiconductor element is disposed on the substrate. The encapsulant covers the semiconductor element. The adhesion layer is disposed on the encapsulant. The metal cap is attached to the encapsulant by the adhesion layer, and the metal cap is conformal with the encapsulant.Type: ApplicationFiled: October 20, 2016Publication date: April 26, 2018Inventors: Ying-Ta CHIU, Chiu-Wen LEE, Dao-Long CHEN, Po-Hsien SUNG, Ping-Feng YANG, Kwang-Lung LIN
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Patent number: 9953930Abstract: A semiconductor package structure includes a substrate, a semiconductor element, an encapsulant, an adhesion layer and a metal cap. The semiconductor element is disposed on the substrate. The encapsulant covers the semiconductor element. The adhesion layer is disposed on the encapsulant. The metal cap is attached to the encapsulant by the adhesion layer, and the metal cap is conformal with the encapsulant.Type: GrantFiled: October 20, 2016Date of Patent: April 24, 2018Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Ying-Ta Chiu, Chiu-Wen Lee, Dao-Long Chen, Po-Hsien Sung, Ping-Feng Yang, Kwang-Lung Lin
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Publication number: 20170278814Abstract: A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent to the surface of the semiconductor element and connected to the trace, and a pillar disposed on the bonding pad. The pillar includes a first end wall, a second end wall opposite the first end wall, a first side wall, and a second side wall opposite the first side wall. The first side wall and the second side wall connect the first end wall to the second end wall. One or both of the first side wall and the second side wall incline inwardly from the first end wall to the second end wall. The pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall.Type: ApplicationFiled: March 22, 2016Publication date: September 28, 2017Inventors: Chih-Pin HUNG, Dao-Long CHEN, Ying-Ta CHIU, Ping-Feng YANG
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Patent number: 9741675Abstract: The present disclosure relates to bump structures and a semiconductor device and semiconductor device package having the same. The semiconductor device includes a body, at least one conductive metal pad and at least one metal pillar. The body includes a first surface. The at least one conductive metal pad is disposed on the first surface. Each metal pillar is formed on a corresponding conductive metal pad. Each metal pillar has a concave side wall and a convex side wall opposite the first concave side wall, and the concave side wall and the convex side wall are orthogonal to the corresponding conductive metal pad.Type: GrantFiled: January 16, 2015Date of Patent: August 22, 2017Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Dao-Long Chen, Ping-Feng Yang, Chang-Chi Lee, Chien-Fan Chen
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Publication number: 20170141007Abstract: The present disclosure relates to a filler composition for a semiconductor package. The filler composition comprises carbon and silica.Type: ApplicationFiled: November 17, 2015Publication date: May 18, 2017Inventors: Ya-Yu HSIEH, Hong-Ping LIN, Dao-Long CHEN, Ping-Feng YANG, Meng-Kai SHIH
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Publication number: 20160358875Abstract: A semiconductor device includes a first circuit layer, a copper pillar disposed adjacent to the first circuit layer, a second circuit layer and a solder layer. The second circuit layer includes an electrical contact and a surface finish layer disposed on the electrical contact, wherein a material of the surface finish layer is a combination of at least two of nickel, gold, and palladium. The solder layer is disposed between the copper pillar and the surface finish layer. The solder layer includes a first intermetallic compound (IMC) and a second IMC, wherein the first IMC includes a combination of two or more of copper, nickel and tin, and the second IMC includes a combination of gold and tin, a combination of palladium and tin, or both.Type: ApplicationFiled: August 17, 2016Publication date: December 8, 2016Inventors: Yu-Hsiang HSIAO, Chiu-Wen LEE, Ping-Feng YANG, Kwang-Lung LIN
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Patent number: 9443813Abstract: The present disclosure relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor die, a semiconductor element and a solder layer. The semiconductor die includes a copper pillar. The semiconductor element includes a surface finish layer, wherein the material of the surface finish layer is a combination of at least two of nickel, gold, and palladium. The solder layer is disposed between the copper pillar and the surface finish layer. The solder layer includes a first intermetallic compound (IMC) and a second IMC, wherein the first IMC includes a combination of at least two of copper, nickel and tin. The second IMC is a combination of gold and tin, a combination of palladium and tin, or both.Type: GrantFiled: March 5, 2015Date of Patent: September 13, 2016Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yu-Hsiang Hsiao, Chiu-Wen Lee, Ping-Feng Yang, Kwang-Lung Lin
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Publication number: 20160260677Abstract: The present disclosure relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes a semiconductor die, a semiconductor element and a solder layer. The semiconductor die includes a copper pillar. The semiconductor element includes a surface finish layer, wherein the material of the surface finish layer is a combination of at least two of nickel, gold, and palladium. The solder layer is disposed between the copper pillar and the surface finish layer. The solder layer includes a first intermetallic compound (IMC) and a second IMC, wherein the first IMC includes a combination of at least two of copper, nickel and tin. The second IMC is a combination of gold and tin, a combination of palladium and tin, or both.Type: ApplicationFiled: March 5, 2015Publication date: September 8, 2016Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yu-Hsiang HSIAO, Chiu-Wen LEE, Ping-Feng YANG, Kwang-Lung LIN
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Publication number: 20160211235Abstract: The present disclosure relates to bump structures and a semiconductor device and semiconductor device package having the same. The semiconductor device includes a body, at least one conductive metal pad and at least one metal pillar. The body includes a first surface. The at least one conductive metal pad is disposed on the first surface. Each metal pillar is formed on a corresponding conductive metal pad. Each metal pillar has a concave side wall and a convex side wall opposite the first concave side wall, and the concave side wall and the convex side wall are orthogonal to the corresponding conductive metal pad.Type: ApplicationFiled: January 16, 2015Publication date: July 21, 2016Inventors: Dao-Long CHEN, Ping-Feng YANG, Chang-Chi LEE, Chien-Fan CHEN
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Publication number: 20120119342Abstract: The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The inner leads of the leads are designed to possess incurved sidewalls for enhancing the adhesion between the inner leads and the surrounding molding compound.Type: ApplicationFiled: November 11, 2010Publication date: May 17, 2012Applicants: MediaTek Inc., ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Pao-Huei Chang Chien, Ping-Cheng Hu, Po-Shing Chiang, Wei-Lun Cheng, Hsueh-Te Wang, Hsiao-Chuan Chang, Tsung-Yueh Tsai, Yi-Shao Lai, Ping-Feng Yang