Patents by Inventor Ping-Heng Yeh

Ping-Heng Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method of electromigration mitigation in stacked IC designs
    Patent number: 9223919
    Abstract: A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, processing the model in a computer processor to generate a temperature map containing temperatures at a plurality of points of the 3D-IC under the operating condition; identifying an electromigration (EM) rating factor, and calculating and outputting from the processor data representing a temperature-dependent EM current constraint at each point.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing, Co., Ltd.
    Inventors: Chi-Yeh Yu, Chung-Min Fu, Ping-Heng Yeh
  • SYSTEM AND METHOD OF ELECTROMIGRATION MITIGATION IN STACKED IC DESIGNS
    Publication number: 20140101626
    Abstract: A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, processing the model in a computer processor to generate a temperature map containing temperatures at a plurality of points of the 3D-IC under the operating condition; identifying an electromigration (EM) rating factor, and calculating and outputting from the processor data representing a temperature-dependent EM current constraint at each point.
    Type: Application
    Filed: December 10, 2013
    Publication date: April 10, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Yeh YU, Chung-Min FU, Ping-Heng YEH
  • System and method of electromigration mitigation in stacked IC designs
    Patent number: 8631372
    Abstract: A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, processing the model in a computer processor to generate a temperature map containing temperatures at a plurality of points of the 3D-IC under the operating condition; identifying an electromigration (EM) rating factor, and calculating and outputting from the processor data representing a temperature-dependent EM current constraint at each point.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Yeh Yu, Chung-Min Fu, Ping-Heng Yeh
  • SYSTEM AND METHOD OF ELECTROMIGRATION MITIGATION IN STACKED IC DESIGNS
    Publication number: 20130212544
    Abstract: A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, processing the model in a computer processor to generate a temperature map containing temperatures at a plurality of points of the 3D-IC under the operating condition; identifying an electromigration (EM) rating factor, and calculating and outputting from the processor data representing a temperature-dependent EM current constraint at each point.
    Type: Application
    Filed: May 22, 2012
    Publication date: August 15, 2013
    Inventors: Chi-Yeh YU, Chung-Min FU, Ping-Heng YEH
  • Table-based DFM for accurate post-layout analysis
    Patent number: 8201111
    Abstract: Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: June 12, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chin Hou, Ying-Chou Cheng, Ru-Gun Liu, Chih-Ming Lai, Yi-Kan Cheng, Chung-Kai Lin, Hsiao-Shu Chao, Ping-Heng Yeh, Min-Hong Wu, Yao-Ching Ku, Tsong-Hua Ou
  • Table-Based DFM for Accurate Post-Layout Analysis
    Publication number: 20110289466
    Abstract: Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.
    Type: Application
    Filed: August 2, 2011
    Publication date: November 24, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Chin Hou, Ying-Chou Cheng, Ru-Gun Liu, Chih-Ming Lai, Yi-Kan Cheng, Chung-Kai Lin, Hsiao-Shu Chao, Ping-Heng Yeh, Min-Hong Wu, Yao-Ching Ku, Tsong-Hua Ou
  • Table-based DFM for accurate post-layout analysis
    Patent number: 8001494
    Abstract: Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.
    Type: Grant
    Filed: October 13, 2008
    Date of Patent: August 16, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chin Hou, Ying-Chou Cheng, Ru-Gun Liu, Chih-Ming Lai, Yi-Kan Cheng, Chung-Kai Lin, Hsiao-Shu Chao, Ping-Heng Yeh, Min-Hong Wu, Yao-Ching Ku, Tsong-Hua Ou
  • TABLE-BASED DFM FOR ACCURATE POST-LAYOUT ANALYSIS
    Publication number: 20100095253
    Abstract: Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.
    Type: Application
    Filed: October 13, 2008
    Publication date: April 15, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Chin HOU, Ying-Chou CHENG, Ru-Gun LIU, Chih-Ming LAI, Yi-Kan CHENG, Chung-Kai LIN, Hsiao-Shu CHAO, Ping-Heng YEH, Min-Hong WU, Yao-Ching KU, Tsong-Hua OU