Patents by Inventor Ping-Ho Lo

Ping-Ho Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6248641
    Abstract: A method of fabricating a shallow trench isolation is disclosed. First, a pad oxide layer and a polysilicon layer are formed on a silicon substrate. The pad oxide layer and the polysilicon layer are etched to expose parts of the substrate. Then the exposed parts of the substrate are oxidized to form an oxide layer. Next, the oxide layer is etched back to form an oxide spacer on the side wall of the polysilicon. Then, a shallow trench is formed by etching the partly exposed substrate. Next, a dielectric layer is formed to fill the shallow trench and then etched back by CMP to stop on the polysilicon layer. Finally, the pad oxide layer and the polysilicon layer are removed. As a result, oxide spacers on the side wall of the shallow trench are formed to eliminate the kink-effect.
    Type: Grant
    Filed: February 5, 1999
    Date of Patent: June 19, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Lu-Min Liu, Hsi-Chieh Chen, Ping-Ho Lo, Sheng-Hao Lin
  • Patent number: 6150273
    Abstract: A method of fabricating kink-effect-free shallow trench isolations is presented in this invention. First, a layer of silicon oxide and a layer of polysilican are sequentially deposited on a substrate, and then shallow trenches are formed, next thermal oxidation is performed to grow a passivation oxide layer on the exposed silicon, and then, a dielectric layer is formed to fill into the shallow trench. Finally, the dielectric layer on the active area is removed by using chemical mechanical polishing and the polysilicon layer provides for the etching end point. The level of shallow trench is higher than the level of active area as soon as stop polishing, because the polysilicon layer is polished faster than dielectric layer. It provides the passivation oxide on the sidewall of shallow trench to form spacers of the active area after removing the polysilicon of active area. It can provide a perfect shallow trench after an oxidation and etching process to avoid the kink effect.
    Type: Grant
    Filed: November 30, 1998
    Date of Patent: November 21, 2000
    Assignee: United Microelectronics Inc.
    Inventors: Lu-Min Liu, Hsi-Chieh Chen, Ping-Ho Lo, Sheng-Hao Lin