Abstract: The present invention provides an analysis method for a semiconductor device for analyzing a plurality of electrical parameters of a HKMG fin field effect transistor and a plurality of process parameters for manufacturing the transistor, comprising: performing key process parameter correlation analysis for each electrical parameter, wherein the key process parameter correlation analysis comprises: constructing multiple electrical-process models of the electrical parameter corresponding to each process parameter respectively; performing sensitivity analysis for each of the electrical-process models; determining a plurality of key process parameters from the plurality of process parameters based on the obtained sensitivity analysis results of the electrical-process models; and determining a relationship between the electrical parameter and the plurality of key process parameters based on a knowledge database.

Abstract: The present disclosure provides an analysis method for a semiconductor device for analyzing a plurality of process parameters for manufacturing a HKMG fin field effect transistor. The analysis method specifically includes: establishing a plurality of process parameter models by grouping the plurality of process parameters in pairs; performing sensitivity analysis on each of the process parameter models; extracting a plurality of key process parameter models from the plurality of process parameter models based on the results of the sensitivity analysis; and performing data mining on the plurality of key process parameter models to determine a plurality of key process parameters and their correlations among the plurality of key process parameters. According to the analysis method provided by the present disclosure, related process parameters are highlighted by data mining and grouping, and the source of process parameter changes is explained. It is possible to adjust the process.

Abstract: The present disclosure provides an analysis method of a semiconductor device, and the semiconductor device comprises a plurality of HKMG fin field effect transistors and a wafer on which the plurality of HKMG fin field effect transistors are located, and the analysis method comprises: performing acceptance testing on the wafer to be tested; constructing an N-type model based on the position of each N-type transistor at the surface of the wafer to be tested and the corresponding acceptance test result, constructing a P-type model based on the position of each P-type transistor at the surface of the wafer to be tested and the corresponding acceptance test result, and constructing an N/P ratio model corresponding to the surface of the wafer to be tested based on the N-type model and the P-type model; and identifying the N/P ratio model based on a preset standard wafer model to determine whether the wafer to be tested is compliant based on the N/P ratio model.

Abstract: The present invention provides an analysis method for a semiconductor device for analyzing a plurality of electrical parameters of a HKMG fin field effect transistor and a plurality of process parameters for manufacturing the transistor, comprising: performing key process parameter correlation analysis for each electrical parameter, wherein the key process parameter correlation analysis comprises: constructing multiple electrical-process models of the electrical parameter corresponding to each process parameter respectively; performing sensitivity analysis for each of the electrical-process models; determining a plurality of key process parameters from the plurality of process parameters based on the obtained sensitivity analysis results of the electrical-process models; and determining a relationship between the electrical parameter and the plurality of key process parameters based on a knowledge database.

Abstract: The present disclosure provides an analysis method for a semiconductor device for analyzing a plurality of process parameters for manufacturing a HKMG fin field effect transistor. The analysis method specifically includes: establishing a plurality of process parameter models by grouping the plurality of process parameters in pairs; performing sensitivity analysis on each of the process parameter models; extracting a plurality of key process parameter models from the plurality of process parameter models based on the results of the sensitivity analysis; and performing data mining on the plurality of key process parameter models to determine a plurality of key process parameters and their correlations among the plurality of key process parameters. According to the analysis method provided by the present disclosure, related process parameters are highlighted by data mining and grouping, and the source of process parameter changes is explained. It is possible to adjust the process.

Abstract: The present disclosure provides an analysis method of a semiconductor device, and the semiconductor device comprises a plurality of HKMG fin field effect transistors and a wafer on which the plurality of HKMG fin field effect transistors are located, and the analysis method comprises: performing acceptance testing on the wafer to be tested; constructing an N-type model based on the position of each N-type transistor at the surface of the wafer to be tested and the corresponding acceptance test result, constructing a P-type model based on the position of each P-type transistor at the surface of the wafer to be tested and the corresponding acceptance test result, and constructing an N/P ratio model corresponding to the surface of the wafer to be tested based on the N-type model and the P-type model; and identifying the N/P ratio model based on a preset standard wafer model to determine whether the wafer to be tested is compliant based on the N/P ratio model.

Abstract: A semiconductor device is provided. First and second pads are electrically connected to a plurality of test structures. Each test structure includes an active region, active patterns, gate electrodes and an electrode pattern. The active region includes a rounded corner portion. The active patterns protrudes from the semiconductor substrate and extends in parallel in a first direction. The gate electrodes crosses over the active patterns in a second direction. One gate electrode is electrically connected to the first pad. The electrode pattern is disposed at a side of the gate electrode electrically connected to the first pad. The electrode pattern is electrically connected to the second pad. The electrode pattern crosses over the active patterns. An overlapping area of the electrode pattern and the active patterns in each test structure is different from an overlapping area of the electrode pattern and the active patterns in other test structures.

Abstract: A semiconductor device is provided. First and second pads are electrically connected to a plurality of test structures. Each test structure includes an active region, active patterns, gate electrodes and an electrode pattern. The active region includes a rounded corner portion. The active patterns protrudes from the semiconductor substrate and extends in parallel in a first direction. The gate electrodes crosses over the active patterns in a second direction. One gate electrode is electrically connected to the first pad. The electrode pattern is disposed at a side of the gate electrode electrically connected to the first pad. The electrode pattern is electrically connected to the second pad. The electrode pattern crosses over the active patterns. An overlapping area of the electrode pattern and the active patterns in each test structure is different from an overlapping area of the electrode pattern and the active patterns in other test structures.

Abstract: A semiconductor device is provided. First and second pads are electrically connected to a plurality of test structures. Each test structure includes an active region, active patterns, gate electrodes and an electrode pattern. The active region includes a rounded corner portion. The active patterns protrudes from the semiconductor substrate and extends in parallel in a first direction. The gate electrodes crosses over the active patterns in a second direction. One gate electrode is electrically connected to the first pad. The electrode pattern is disposed at a side of the gate electrode electrically connected to the first pad. The electrode pattern is electrically connected to the second pad. The electrode pattern crosses over the active patterns. An overlapping area of the electrode pattern and the active patterns in each test structure is different from an overlapping area of the electrode pattern and the active patterns in other test structures.

Abstract: A semiconductor device is provided. First and second pads are electrically connected to a plurality of test structures. Each test structure includes an active region, active patterns, gate electrodes and an electrode pattern. The active region includes a rounded corner portion. The active patterns protrudes from the semiconductor substrate and extends in parallel in a first direction. The gate electrodes crosses over the active patterns in a second direction. One gate electrode is electrically connected to the first pad. The electrode pattern is disposed at a side of the gate electrode electrically connected to the first pad. The electrode pattern is electrically connected to the second pad. The electrode pattern crosses over the active patterns. An overlapping area of the electrode pattern and the active patterns in each test structure is different from an overlapping area of the electrode pattern and the active patterns in other test structures.