Abstract: A chip package with COB configuration is disclosed. A thin film substrate as a carrier of a wire-bonded chip has a slot, wherein the electrical connection between the chip and the thin film substrate are a plurality of bonding wires through the slot. The thin film substrate includes a patterned metal core with resin and at least a solder resist layer on the patterned metal core, wherein the patterned metal core has a plurality of finger pads and a plurality of ball pads. The finger pads are disposed around the slot. When the active surface of the chip is attached to the thin film substrate, the patterned metal core provides a good thermal dissipation for the chip. Moreover, the chip package using thin film substrates can reduce the cost of the substrate and the overall thickness of the package and enhance the cushion effect against thermal stress.

Abstract: A method for computer-aided plate punching is disclosed. The method includes the steps of reading and configuring processing data; reading a design drawing of a workpiece as a processing diagram; selecting needed figures from the processing diagram, and configuring template attributes to confirm contour of the workpiece; selecting operation modes and cutters for processing orifices; processing the orifices and generating cutters information; selecting operation modes and cutters for processing slots; processing the slots and generating cutters information; optimizing the cutters information, and generating a list of cutters; and converting the list of cutters into corresponding CNC codes. A related system is also disclosed.

Abstract: A wafer heater is provided, including a body also serving as a heat source, a ceramic ring on the body, and a buffer ring on the body. The buffer ring contacts with the ceramic ring, and has a top surface higher than that of the ceramic ring so that a wafer can be placed on the top surface of the buffer ring without contacting the ceramic ring. The thermal conductivity coefficient of the buffer ring is smaller than that of the ceramic ring. The product of thermal conductivity coefficient and top surface area of the buffer ring is also smaller than that of the ceramic ring.

Abstract: A transistor structure is manufactured for ESD protection in an integrated circuit device. A semiconductor substrate has source and drain diffusion regions and respective source and drain wells under the source and drain diffusion regions. A shallow trench isolation formed over the semiconductor substrate and into the semiconductor substrate separates the source and drain diffusion regions and a portion of the source and drain wells. Source and drain contact structures respectively formed on the shallow trench isolation over the source and drain diffusion regions and extend through the shallow trench isolation to contact the source and drain diffusion regions. An ion implantation is performed through the contact openings into the bottoms of the source and drain wells to control the device trigger voltage and position the discharge current far away from the surface, which increases the device ESD performance significantly.

Abstract: Disclosed is an automated disk-ejection apparatus for use in a disk system. The disk system includes a disk box for housing a disk drive, and the auto-ejection apparatus comprises: a handle for pulling out or pushing back the disk box; a pushing mechanism for pushing the handle; and a control circuit for controlling the pushing mechanism. The featured disk apparatus is designed such that while the disk box needs to be pulled out in order for loading or replacing the disk drive, the pushing mechanism is activated to push the handle. The handle can thus be rotated along the pivot into an inoperative state, for subsequently to be pulled for withdrawing the disk box. Moreover, another embodiment of the present invention relates to using a pushing mechanism to push a rotatable panel of a disk box.

Abstract: A transistor structure is provided for ESD protection in an integrated circuit device. A semiconductor substrate has source and drain diffusion regions and respective source and drain wells under the source and drain diffusion regions. A shallow trench isolation formed over the semiconductor substrate and into the semiconductor substrate separates the source and drain diffusion regions and a portion of the source and drain wells. Source and drain contact structures respectively formed on the shallow trench isolation over the source and drain diffusion regions and extend through the shallow trench isolation to contact the source and drain diffusion regions. An ion implantation is performed through the contact openings into the bottoms of the source and drain wells to control the device trigger voltage and position the discharge current far away from the surface, which increases the device ESD performance significantly.

Abstract: A transistor structure is provided for ESD protection in an integrated circuit device. A semiconductor substrate has source and drain diffusion regions and respective source and drain wells under the source and drain diffusion regions. A shallow trench isolation formed over the semiconductor substrate and into the semiconductor substrate separates the source and drain diffusion regions and a portion of the source and drain wells. Source and drain contact structures respectively formed on the shallow trench isolation over the source and drain diffusion regions and extend through the shallow trench isolation to contact the source and drain diffusion regions. An ion implantation is performed through the contact openings into the bottoms of the source and drain wells to control the device trigger voltage and position the discharge current far away from the surface, which increases the device ESD performance significantly.

Abstract: Described is a MOS gate-controlled SCR (UGSCR) structure with a U-shaped gate (UMOS) for an ESD protection circuit in an IC device which is compatible with shallow trench isolation (STI) and self-aligned silicide (salicide) fabrication technology. The UMOS gate is located in a p-substrate and is surrounded by an n-well on either side. Adjacent to one side of the UMOS gate, a first n+ diffusion is formed which straddles the first n-well. The n+ diffusion together with a p+ pickup diffused next to it form the cathode of the SCR (thyristor). Adjacent to the other side of the UMOS gate, a second n+ and p+ diffusion are formed in a second n-well. The second n+ and p+ diffusion together with the UMOS gate form the anode of the SCR and the input terminal of the circuit to be protected. The SCR is formed by the first n+ diffusion/n-well (cathode), the p-substrate, the second n-well and the second p+/n+ diffusion (anode).

Abstract: A structure of a lockset is disclosed. The lockset structure includes a key and a lock body, wherein the key and the lock hole of the latch are provided with at least one end corner having a skew face with a corresponding angle. Any key with un-matching angle is prevented from inserting into the lock hole so as to avoid other parties to open the lockset with un-matching keys.

Abstract: A structure of a lockset is disclosed. The lockset structure includes a key and a lock body, wherein the key and the lock hole of the latch are provided with at least one end corner having a skew face with a corresponding angle. Any key with un-matching angle is prevented from inserting into the lock hole so as to avoid other parties to open the lockset with un-matching keys.

Abstract: Described is a MOS gate-controlled SCR (UGSCR) structure with a U-shaped gate (UMOS) for an ESD protection circuit in an IC device which is compatible with shallow trench isolation (STI) and self-aligned silicide (salicide) fabrication technology. The UMOS gate is located in a p-substrate and is surrounded by an n-well on either side. Adjacent to one side of the UMOS gate, a first n+ diffusion is formed which straddles the first n-well. The n+ diffusion together with a p+ pickup diffused next to it form the cathode of the SCR (thyristor). Adjacent to the other side of the UMOS gate, a second n+ and p+ diffusion are formed in a second n-well. The second n+ and p+ diffusion together with the UMOS gate form the anode of the SCR and the input terminal of the circuit to be protected. The SCR is formed by the first n+ diffusion/n-well (cathode), the p-substrate, the second n-well and the second p+/n+ diffusion (anode).

Abstract: Described is a method of creating a MOS gate-controlled SCR (UGSCR) structure with a U-shaped gate (UMOS) for an ESD protection circuit in an IC device which is compatible with shallow trench isolation (STI) and self-aligned silicide (salicide) fabrication technology. The UMOS gate is located in a p-substrate and is surrounded by an n-well on either side. Adjacent to one side of the UMOS gate, a first n+ diffusion is formed which straddles the first n-well. The n+ diffusion together with a p+ pickup diffused next to it form the cathode of the SCR (thyristor). Adjacent to the other side of the UMOS gate, a second n+ and p+ diffusion are formed in a second n-well. The second n+ and p+ diffusion together with the UMOS gate form the anode of the SCR and the input terminal of the circuit to be protected. The SCR is formed by the first n+ diffusion/n-well (cathode), the p-substrate, the second n-well and the second p+/n+ diffusion (anode).

Abstract: Described is a MOS gate-controlled SCR (UGSCR) structure with a U-shaped gate (UMOS) for an ESD protection circuit in an IC device which is compatible with shallow trench isolation (STI) and self-aligned suicide (salicide) fabrication technology. The UMOS gate is located in a p-substrate and is surrounded by an n-well on either side. Adjacent to one side of the UMOS gate, a first n+ diffusion is formed which straddles the first n-well. The n+ diffusion together with a p+ pickup diffused next to it form the cathode of the SCR (thyristor). Adjacent to the other side of the UMOS gate, a second n+ and p+ diffusion are formed in a second n-well. The second n+ and p+ diffusion together with the UMOS gate form the anode of the SCR and the input terminal of the circuit to be protected. The SCR is formed by the first n+ diffusion/n-well (cathode), the p-substrate, the second n-well and the second p+ /n+diffusion (anode).

Abstract: Disclosed is an automated disk-ejection apparatus for use in a disk system. The disk system includes a disk box for housing a disk drive, and the auto-ejection apparatus comprises: a handle for pulling out or pushing back the disk box; a pushing mechanism for pushing the handle; and a control circuit for controlling the pushing mechanism. The featured disk apparatus is designed such that while the disk box needs to be pulled out in order for loading or replacing the disk drive, the pushing mechanism is activated to push the handle. The handle can thus be rotated along the pivot into an inoperative state, for subsequently to be pulled for withdrawing the disk box. Moreover, another embodiment of the present invention relates to using a pushing mechanism to push a rotatable panel of a disk box.

Abstract: A transistor structure is provided for ESD protection in an integrated circuit device. A semiconductor substrate has source and drain diffusion regions and respective source and drain wells under the source and drain diffusion regions. A shallow trench isolation formed over the semiconductor substrate and into the semiconductor substrate separates the source and drain diffusion regions and a portion of the source and drain wells. Source and drain contact structures respectively formed on the shallow trench isolation over the source and drain diffusion regions and extend through the shallow trench isolation to contact the source and drain diffusion regions. An ion implantation is performed through the contact openings into the bottoms of the source and drain wells to control the device trigger voltage and position the discharge current far away from the surface, which increases the device ESD performance significantly.

Abstract: A sequence of angiographic images is made up of frames of data. A sample sequence, made up of a number of such frames, is compressed using a lower value of the quantization factor and the resulting average compression ratio is determined. The same sample sequence is also compressed using a higher value for the quantization factor and another average compression ratio is determined. The value of the quantization factor corresponding to a desired average compression ratio of the entire sequence can then be determined by linear interpolation.

Abstract: Controlling the stepping of an x-ray angiography imaging device (and/or table), and/or providing a visualization aid for stepping an x-ray angiography imaging device (and/or table), to maximize the diagnostic usefulness of images acquired by the x-ray angiography imaging device. The stepping and visualization aid use features, extracted from captured images, of the state of contrast media injected into a patient.

Abstract: Controlling the stepping of an x-ray angiography imaging device (and/or table), and/or providing a visualization aid for stepping an x-ray angiography imaging device (and/or table), to maximize the diagnostic usefulness of images acquired by the x-ray angiography imaging device. The stepping and visualization aid use features, extracted from captured images, of the state of contrast media injected into a patient.

Abstract: A method to form shallow trench isolation structures with improved isolation fill and surface planarity is described. A pad oxide layer is provided over the surface of a semiconductor substrate. A silicon nitride layer is deposited overlying the pad oxide layer. A thin oxide layer is deposited overlying the silicon nitride layer. An isolation trench is etched through the thin oxide layer, the nitride layer, and the pad oxide layer and into the substrate. The silicon nitride layer exposed within the trench is etched to form a lateral undercut leaving a projection of the thin oxide layer and exposing a portion of the underlying pad oxide layer. The thin oxide layer and the exposed portion of the pad oxide layer are etched away thereby exposing portions of the surface of the substrate. A liner oxide is grown on the exposed portions of the semiconductor substrate within the isolation trench and on the surface of the substrate.

Abstract: A safety apparatus of a piezoelectric lighter includes a pressure absorbing device disposed in a cap cavity of a casing of the piezoelectric lighter, a holding means integrally affixed to an interior surface of a thumb-push cap for rigidly holding one end of the pressure absorbing device in position, and a receiving means provided in the cap cavity for receiving and supporting another end of the pressure absorbing device in position. Therefore the pressure absorbing device is vertically held between the thumb-push cap and the ceiling of the casing for urging the thumb-push cap at an upper normal position thereof and providing an additional press resistance to the thumb-push cap, so as to resist a downwardly press force applied by an under age child on the thumb-push cap while an adult is capable of pushing down the thumb-push cap easily.