Abstract: A method of manufacturing a semiconductor structure with flush shallow trench isolation and gate oxide, including performing a first etching process to remove a pad oxide layer at one side of a STI and recess the substrate, the first etching process also forms a recess portion not covered by the first etching process and a protruding portion covered by the first etching process on the STI, forming a gate oxide layer on the recessed substrate, performing a second etching process to remove the protruding portion and the pad oxide layer and a first oxide layer on a drain region, performing a third etching process to remove a part of the STI and a second oxide layer, so that a top plane of the STI is flush with the gate oxide layer.

Abstract: A semiconductor structure includes a substrate having a first device region and a second device region in proximity to the first device region. A first trench isolation structure is disposed in the substrate between the first device region and the second device region. The first trench isolation structure includes a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is lower than the second bottom surface. The first trench isolation structure includes a first top surface within the first device region and a second top surface within the second device region. The first top surface is coplanar with the second top surface.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The configuration specifies a bundle size N. Modulation symbols in N consecutive PRBs are precoded with a same precoder. The UE determines whether a precoding condition is true. The precoding condition is that modulation symbols in a first set of resources and a second set of resources are precoded with a same precoder. Each set of the first set of resources and the second set of resources contains N PRBs. When the precoding condition is met: the UE measures reference signals in the second set of resources; the UE determines a channel condition of the first set of resources in consideration of the measurements of the reference signals in the second set of resources.

Abstract: A BJT device includes a substrate of first conductive type; a first ion well of second conductive type located in the substrate; a second ion well of first conductive type located in the first ion well; an emitter region of second conductive type located in the second ion well; a first trench isolation region surrounding the emitter region; a base region of first conductivity type located in the second ion well; a second trench isolation region surrounding the base region; a third ion well of second conductivity type located in the first ion well and surrounding the second ion well; and a collector region of second conductivity type located in the third ion well and surrounding the second trench isolation region. The junction depth of the emitter region is deeper than the junction depth of the base region or the junction depth of the collector region.

Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first drift region, a gate structure, a first sub gate structure, a first spacer structure, a second spacer structure, and a first insulation structure. The first drift region is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate and separated from the first sub gate structure. The first sub gate structure and the first insulation structure are disposed on the first drift region. The first spacer structure is disposed on a sidewall of the gate structure. The second spacer structure is disposed on a sidewall of the first sub gate structure. At least a part of the first insulation structure is located between the first spacer structure and the second spacer structure. The first insulation structure is directly connected with the first drift region located between the first spacer structure and the second spacer structure.

Abstract: A semiconductor structure includes a substrate having a first device region and a second device region in proximity to the first device region. A trench isolation structure is disposed in the substrate between the first device region and the second device region. The trench isolation structure includes a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is coplanar with the second bottom surface.

Abstract: A semiconductor device includes a substrate, a first oxide layer and a second oxide layer. The substrate has a first region and a second region. The first oxide layer is disposed on the first region. The first oxide layer includes a first thermal oxide layer and a first deposited oxide layer, and a portion of the first thermal oxide layer is formed by a pad oxide layer. The second oxide layer is disposed on the second region. The second oxide layer includes a second thermal oxide layer and a second deposited oxide layer.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first recess and a second recess are formed in a first region and a second region of a semiconductor substrate, respectively. A bottom surface of the first recess is lower than a bottom surface of the second recess in a vertical direction. A first gate oxide layer and a second gate oxide layer are formed concurrently. At least a portion of the first gate oxide layer is formed in the first recess, and at least a portion of the second gate oxide layer is formed in the second recess. A removing process is performed for removing a part of the second gate oxide layer. A thickness of the second gate oxide layer is less than a thickness of the first gate oxide layer after the removing process.

Abstract: A method of manufacturing a semiconductor structure with flush shallow trench isolation and gate oxide, including performing a first etching process to remove a pad oxide layer at one side of a STI and recess the substrate, the first etching process also forms a recess portion not covered by the first etching process and a protruding portion covered by the first etching process on the STI, forming a gate oxide layer on the recessed substrate, performing a second etching process to remove the protruding portion and the pad oxide layer and a first oxide layer on a drain region, performing a third etching process to remove a part of the STI and a second oxide layer, so that a top plane of the STI is flush with the gate oxide layer.

Abstract: A semiconductor structure includes a substrate having a first device region and a second device region in proximity to the first device region. A trench isolation structure is disposed in the substrate between the first device region and the second device region. The trench isolation structure includes a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is coplanar with the second bottom surface.

Abstract: Semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor, a second transistor, a third transistor, and a plurality of shallow trench isolations. The first transistor is disposed in a medium-voltage region and includes a first plane, a first gate dielectric layer, and a first gate electrode. The second transistor is disposed in a boundary region and includes a second plane, a second gate dielectric layer, and a second gate electrode. The third transistor is disposed in a lower-voltage region and includes a third plane, a third gate dielectric layer, and a third gate electrode. The shallow trench isolations are disposed in the substrate, wherein top surfaces of the shallow trench isolations in the medium-voltage region, the boundary region and the low-voltage region are coplanar with top surfaces of the first gate dielectric layer and the second gate dielectric layer.

Abstract: A method for handling radio link monitoring (RLM) includes: receiving downlink (DL) data from a network device; performing a first measurement according to the DL data, to generate a first measurement result of the DL data; comparing the first measurement result and a first threshold, to determine a first indication; comparing the first measurement result and a second threshold, to determine a second indication; and determining whether a radio link failure (RLF) occurs according to at least one of the first indication and the second indication.

Abstract: The invention provides a method for forming a semiconductor structure, which comprises providing a substrate, sequentially a first groove and a second groove are formed in the substrate, the depth of the first groove is different from the depth of the second groove, a first oxide layer is formed in the first groove, a second oxide layer is formed in the second groove, an etching step is performed to remove part of the first oxide layer, a first gate structure is formed on the first oxide layer, and a second gate structure is formed on the second oxide layer.

Abstract: A semiconductor structure includes a substrate having a first device region and a second device region in proximity to the first device region. A first trench isolation structure is disposed in the substrate between the first device region and the second device region. The first trench isolation structure includes a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is lower than the second bottom surface. The first trench isolation structure includes a first top surface within the first device region and a second top surface within the second device region. The first top surface is coplanar with the second top surface.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The configuration specifies a bundle size N. Modulation symbols in N consecutive PRBs are precoded with a same precoder. The UE determines whether a precoding condition is true. The precoding condition is that modulation symbols in a first set of resources and a second set of resources are precoded with a same precoder. Each set of the first set of resources and the second set of resources contains N PRBs. When the precoding condition is met: the UE measures reference signals in the second set of resources; the UE determines a channel condition of the first set of resources in consideration of the measurements of the reference signals in the second set of resources.

Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first drift region, a gate structure, a first sub gate structure, a first spacer structure, a second spacer structure, and a first insulation structure. The first drift region is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate and separated from the first sub gate structure. The first sub gate structure and the first insulation structure are disposed on the first drift region. The first spacer structure is disposed on a sidewall of the gate structure. The second spacer structure is disposed on a sidewall of the first sub gate structure. At least a part of the first insulation structure is located between the first spacer structure and the second spacer structure. The first insulation structure is directly connected with the first drift region located between the first spacer structure and the second spacer structure.

Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first drift region, a gate structure, a first sub gate structure, a first spacer structure, a second spacer structure, and a first insulation structure. The first drift region is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate and separated from the first sub gate structure. The first sub gate structure and the first insulation structure are disposed on the first drift region. The first spacer structure is disposed on a sidewall of the gate structure. The second spacer structure is disposed on a sidewall of the first sub gate structure. At least a part of the first insulation structure is located between the first spacer structure and the second spacer structure. The first insulation structure is directly connected with the first drift region located between the first spacer structure and the second spacer structure.

Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first drift region, a gate structure, a first sub gate structure, a first spacer structure, a second spacer structure, and a first insulation structure. The first drift region is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate and separated from the first sub gate structure. The first sub gate structure and the first insulation structure are disposed on the first drift region. The first spacer structure is disposed on a sidewall of the gate structure. The second spacer structure is disposed on a sidewall of the first sub gate structure. At least a part of the first insulation structure is located between the first spacer structure and the second spacer structure. The first insulation structure is directly connected with the first drift region located between the first spacer structure and the second spacer structure.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first recess and a second recess are formed in a first region and a second region of a semiconductor substrate, respectively. A bottom surface of the first recess is lower than a bottom surface of the second recess in a vertical direction. A first gate oxide layer and a second gate oxide layer are formed concurrently. At least a portion of the first gate oxide layer is formed in the first recess, and at least a portion of the second gate oxide layer is formed in the second recess. A removing process is performed for removing a part of the second gate oxide layer. A thickness of the second gate oxide layer is less than a thickness of the first gate oxide layer after the removing process.

Abstract: Semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor, a second transistor, a third transistor, and a plurality of shallow trench isolations. The first transistor is disposed in a medium-voltage region and includes a first plane, a first gate dielectric layer, and a first gate electrode. The second transistor is disposed in a boundary region and includes a second plane, a second gate dielectric layer, and a second gate electrode. The third transistor is disposed in a lower-voltage region and includes a third plane, a third gate dielectric layer, and a third gate electrode. The shallow trench isolations are disposed in the substrate, wherein top surfaces of the shallow trench isolations in the medium-voltage region, the boundary region and the low-voltage region are coplanar with top surfaces of the first gate dielectric layer and the second gate dielectric layer.