Patents by Inventor Ping-Hung Chiang
Ping-Hung Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923435Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first drift region, a gate structure, a first sub gate structure, a first spacer structure, a second spacer structure, and a first insulation structure. The first drift region is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate and separated from the first sub gate structure. The first sub gate structure and the first insulation structure are disposed on the first drift region. The first spacer structure is disposed on a sidewall of the gate structure. The second spacer structure is disposed on a sidewall of the first sub gate structure. At least a part of the first insulation structure is located between the first spacer structure and the second spacer structure. The first insulation structure is directly connected with the first drift region located between the first spacer structure and the second spacer structure.Type: GrantFiled: April 18, 2022Date of Patent: March 5, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hsin-Han Wu, Kai-Kuen Chang, Ping-Hung Chiang
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Publication number: 20230307524Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first drift region, a gate structure, a first sub gate structure, a first spacer structure, a second spacer structure, and a first insulation structure. The first drift region is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate and separated from the first sub gate structure. The first sub gate structure and the first insulation structure are disposed on the first drift region. The first spacer structure is disposed on a sidewall of the gate structure. The second spacer structure is disposed on a sidewall of the first sub gate structure. At least a part of the first insulation structure is located between the first spacer structure and the second spacer structure. The first insulation structure is directly connected with the first drift region located between the first spacer structure and the second spacer structure.Type: ApplicationFiled: April 18, 2022Publication date: September 28, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hsin-Han Wu, Kai-Kuen Chang, Ping-Hung Chiang
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Publication number: 20230231035Abstract: A manufacturing method of a semiconductor device includes the following steps. A first recess and a second recess are formed in a first region and a second region of a semiconductor substrate, respectively. A bottom surface of the first recess is lower than a bottom surface of the second recess in a vertical direction. A first gate oxide layer and a second gate oxide layer are formed concurrently. At least a portion of the first gate oxide layer is formed in the first recess, and at least a portion of the second gate oxide layer is formed in the second recess. A removing process is performed for removing a part of the second gate oxide layer. A thickness of the second gate oxide layer is less than a thickness of the first gate oxide layer after the removing process.Type: ApplicationFiled: February 17, 2022Publication date: July 20, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wei-Lun Huang, Chia-Ling Wang, Chia-Wen Lu, Ta-Wei Chiu, Ping-Hung Chiang
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Publication number: 20230223306Abstract: Semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor, a second transistor, a third transistor, and a plurality of shallow trench isolations. The first transistor is disposed in a medium-voltage region and includes a first plane, a first gate dielectric layer, and a first gate electrode. The second transistor is disposed in a boundary region and includes a second plane, a second gate dielectric layer, and a second gate electrode. The third transistor is disposed in a lower-voltage region and includes a third plane, a third gate dielectric layer, and a third gate electrode. The shallow trench isolations are disposed in the substrate, wherein top surfaces of the shallow trench isolations in the medium-voltage region, the boundary region and the low-voltage region are coplanar with top surfaces of the first gate dielectric layer and the second gate dielectric layer.Type: ApplicationFiled: February 15, 2022Publication date: July 13, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ta-Wei Chiu, Ping-Hung Chiang, Chia-Wen Lu, Chia-Ling Wang, Wei-Lun Huang
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Publication number: 20230207620Abstract: A semiconductor structure includes a substrate having a first device region and a second device region in proximity to the first device region. A trench isolation structure is disposed in the substrate between the first device region and the second device region. The trench isolation structure includes a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is coplanar with the second bottom surface.Type: ApplicationFiled: January 18, 2022Publication date: June 29, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chia-Ling Wang, Ping-Hung Chiang, Wei-Lun Huang, Chia-Wen Lu, Ta-Wei Chiu
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Publication number: 20230080968Abstract: The invention provides a method for forming a semiconductor structure, which comprises providing a substrate, sequentially a first groove and a second groove are formed in the substrate, the depth of the first groove is different from the depth of the second groove, a first oxide layer is formed in the first groove, a second oxide layer is formed in the second groove, an etching step is performed to remove part of the first oxide layer, a first gate structure is formed on the first oxide layer, and a second gate structure is formed on the second oxide layer.Type: ApplicationFiled: October 6, 2021Publication date: March 16, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wei-Lun Huang, Chia-Ling Wang, Chia-Wen Lu, Ping-Hung Chiang
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Publication number: 20210119014Abstract: A high voltage semiconductor device and a manufacturing method thereof are provided in the present invention. A recess is formed in a semiconductor substrate, and a gate dielectric layer and a main gate structure are formed in the recess. Therefore, the high voltage semiconductor device formed by the manufacturing method of the present invention may include the main gate structure lower than a top surface of an isolation structure formed in the semiconductor substrate. Problems about integrated manufacturing processes of the high voltage semiconductor device and other kinds of semiconductor devices when the gate structure is relatively high because of the thicker gate dielectric layer required in the high voltage semiconductor device may be improved accordingly.Type: ApplicationFiled: December 9, 2020Publication date: April 22, 2021Inventors: Shih-Yin Hsiao, Kuan-Liang Liu, Ching-Chung Yang, Ping-Hung Chiang
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Patent number: 10903334Abstract: A high voltage semiconductor device and a manufacturing method thereof are provided in the present invention. A recess is formed in a semiconductor substrate, and a gate dielectric layer and a main gate structure are formed in the recess. Therefore, the high voltage semiconductor device formed by the manufacturing method of the present invention may include the main gate structure lower than a top surface of an isolation structure formed in the semiconductor substrate. Problems about integrated manufacturing processes of the high voltage semiconductor device and other kinds of semiconductor devices when the gate structure is relatively high because of the thicker gate dielectric layer required in the high voltage semiconductor device may be improved accordingly.Type: GrantFiled: March 10, 2020Date of Patent: January 26, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Yin Hsiao, Kuan-Liang Liu, Ching-Chung Yang, Ping-Hung Chiang
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Publication number: 20200212201Abstract: A high voltage semiconductor device and a manufacturing method thereof are provided in the present invention. A recess is formed in a semiconductor substrate, and a gate dielectric layer and a main gate structure are formed in the recess. Therefore, the high voltage semiconductor device formed by the manufacturing method of the present invention may include the main gate structure lower than a top surface of an isolation structure formed in the semiconductor substrate. Problems about integrated manufacturing processes of the high voltage semiconductor device and other kinds of semiconductor devices when the gate structure is relatively high because of the thicker gate dielectric layer required in the high voltage semiconductor device may be improved accordingly.Type: ApplicationFiled: March 10, 2020Publication date: July 2, 2020Inventors: Shih-Yin Hsiao, Kuan-Liang Liu, Ching-Chung Yang, Ping-Hung Chiang
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Patent number: 10629697Abstract: A high voltage semiconductor device and a manufacturing method thereof are provided in the present invention. A recess is formed in a semiconductor substrate, and a gate dielectric layer and a main gate structure are formed in the recess. Therefore, the high voltage semiconductor device formed by the manufacturing method of the present invention may include the main gate structure lower than a top surface of an isolation structure formed in the semiconductor substrate. Problems about integrated manufacturing processes of the high voltage semiconductor device and other kinds of semiconductor devices when the gate structure is relatively high because of the thicker gate dielectric layer required in the high voltage semiconductor device may be improved accordingly.Type: GrantFiled: November 15, 2016Date of Patent: April 21, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Yin Hsiao, Kuan-Liang Liu, Ching-Chung Yang, Ping-Hung Chiang
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Patent number: 10475903Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.Type: GrantFiled: January 28, 2019Date of Patent: November 12, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Ling Wang, Ping-Hung Chiang, Chang-Po Hsiung, Chia-Wen Lu, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
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Patent number: 10453938Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.Type: GrantFiled: December 18, 2017Date of Patent: October 22, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Ling Wang, Ping-Hung Chiang, Chang-Po Hsiung, Chia-Wen Lu, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
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Patent number: 10411088Abstract: A semiconductor device including a substrate and a shallow trench isolation (STI) structure is provided. The substrate has a first voltage area and a second voltage area. A top surface of the substrate in the second voltage area is higher than a top surface of the substrate in the first voltage area, and a trench is defined in the substrate in between the first and second voltage area. The STI structure is located in the substrate within the trench, wherein a first portion of the STI structure is located in the first voltage area, a second portion of the STI structure is located in the second voltage area, and a step height difference exist in between a bottom surface of the first portion of the STI structure in the first voltage area and a bottom surface of the second portion of the STI structure in the second voltage area.Type: GrantFiled: April 12, 2018Date of Patent: September 10, 2019Assignee: United Microelectronics Corp.Inventors: Chang-Po Hsiung, Ping-Hung Chiang, Shih-Chieh Pu, Chia-Lin Wang, Nien-Chung Li, Wen-Fang Lee, Shih-Yin Hsiao, Chih-Chung Wang
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Publication number: 20190157421Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.Type: ApplicationFiled: January 28, 2019Publication date: May 23, 2019Inventors: Chia-Ling Wang, Ping-Hung Chiang, Chang-Po Hsiung, Chia-Wen Lu, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
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Publication number: 20190157418Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.Type: ApplicationFiled: December 18, 2017Publication date: May 23, 2019Inventors: Chia-Ling Wang, Ping-Hung Chiang, Chang-Po Hsiung, Chia-Wen Lu, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
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Publication number: 20190103460Abstract: A semiconductor transistor device is provided. The semiconductor transistor device includes a semiconductor substrate, a gate structure, a first isolation structure, a first doped region, and a first extra-contact structure. The gate structure is disposed on the semiconductor substrate, and the semiconductor substrate has a first region and a second region respectively located on two opposite sides of the gate structure. The first isolation structure and the first doped region are disposed in the first region of the semiconductor substrate. The first extra-contact structure is disposed on the semiconductor structure. The first extra-contact structure is located between the gate structure and the first doped region and penetrating into the first isolation structure in the first region of the semiconductor substrate, and the first doped region is electrically coupled to the first extra-contact structure.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Inventors: Chang-Po Hsiung, Ping-Hung Chiang, Chia-Lin Wang, Chia-Wen Lu, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
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Publication number: 20180233556Abstract: A semiconductor device including a substrate and a shallow trench isolation (STI) structure is provided. The substrate has a first voltage area and a second voltage area. A top surface of the substrate in the second voltage area is higher than a top surface of the substrate in the first voltage area, and a trench is defined in the substrate in between the first and second voltage area. The STI structure is located in the substrate within the trench, wherein a first portion of the STI structure is located in the first voltage area, a second portion of the STI structure is located in the second voltage area, and a step height difference exist in between a bottom surface of the first portion of the STI structure in the first voltage area and a bottom surface of the second portion of the STI structure in the second voltage area.Type: ApplicationFiled: April 12, 2018Publication date: August 16, 2018Applicant: United Microelectronics Corp.Inventors: Chang-Po Hsiung, Ping-Hung Chiang, Shih-Chieh Pu, Chia-Lin Wang, Nien-Chung Li, Wen-Fang Lee, Shih-Yin Hsiao, Chih-Chung Wang
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Patent number: 9985129Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.Type: GrantFiled: November 22, 2017Date of Patent: May 29, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Yin Hsiao, Kuan-Liang Liu, Ching-Chung Yang, Kai-Kuen Chang, Ping-Hung Chiang, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
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Patent number: 9973254Abstract: A communications apparatus and method are provided. The communications method for an apparatus capable of Carrier Aggregation (CA), wherein the apparatus includes a plurality of processing engines and antennas, includes the steps of determining whether the apparatus is configured in a single component carrier for a first group of the antennas, and activating a second group of the antennas when the apparatus is configured in the single component carrier. T the first group of antennas are configured for a first part of the processing engines and the second group of antennas are configured for a second part of the processing engines, and the first part of the processing engines and the second part of the processing engines share a MIMO detector.Type: GrantFiled: December 27, 2016Date of Patent: May 15, 2018Assignee: MEDIATEK INC.Inventors: Po-Ying Chen, Wei-De Wu, Ping-Hung Chiang, Mao-Ching Chiu
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Patent number: 9972678Abstract: A method of forming a semiconductor device is provided including the following steps. A substrate having a first voltage area and a second voltage area is provided. A first oxide layer is formed in the first voltage area. The first oxide layer is removed to form a recess in the first voltage area. A shallow trench isolation (STI) structure is formed in the substrate, wherein a first portion of the STI structure is located in the first voltage area and a second portion of the STI structure is located in the second voltage area, a top surface of the STI structure is higher than the top surface of the substrate, and a bottom surface of the first portion of the STI structure in the first voltage area is lower than a bottom surface of the second portion of the STI structure in the second voltage area.Type: GrantFiled: October 6, 2016Date of Patent: May 15, 2018Assignee: United Microelectronics Corp.Inventors: Chang-Po Hsiung, Ping-Hung Chiang, Shih-Chieh Pu, Chia-Lin Wang, Nien-Chung Li, Wen-Fang Lee, Shih-Yin Hsiao, Chih-Chung Wang