Patents by Inventor Ping-Hung Shih

Ping-Hung Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11574935
    Abstract: A pixel array substrate, including gate elements and transfer elements, is provided. The gate elements include an n-th gate element and an m-th gate element. The transfer elements include a n-th transfer element and an m-th transfer element electrically connected to the n-th gate element and the m-th gate element respectively. A peripheral portion of each of the transfer elements includes a first straight section. A peripheral portion of the n-th transfer element further includes a first lateral section. The first lateral section of the n-th transfer element and the first straight section of the n-th transfer element respectively belong to a first conductive layer and a second conductive layer. A peripheral portion of the m-th transfer element crosses over the first lateral section of the peripheral portion of the n-th transfer element.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: February 7, 2023
    Assignee: Au Optronics Corporation
    Inventors: Min-Tse Lee, Sheng-Yen Cheng, Yueh-Hung Chung, Ya-Ling Hsu, Chen-Hsien Liao, Peng-Che Tai, Ping-Hung Shih
  • Patent number: 11506923
    Abstract: A display panel includes a substrate, a plurality of standard pixel units, and a plurality of dummy pixel units. A plurality of first conductor patterns and a plurality of shield blocks of a shield pattern layer are arranged in an array above the substrate. Each of the standard pixel units includes one of the first conductor patterns and a first shield block of the shield blocks. The first shield blocks and the first conductor patterns are overlapped, respectively. Each of the dummy pixel units includes a second shield block of the shield blocks. The second shield blocks and the first conductor patterns are not overlapped. A first edge of the substrate is spaced apart from a second edge of one of the standard pixel units adjacent to the dummy pixel units by a first distance. The first distance is within a range from 50 ?m to 3000 ?m.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: November 22, 2022
    Assignee: Au Optronics Corporation
    Inventors: Ping-Hung Shih, Wei-Chieh Sun, Peng-Che Tai, Chia-Heng Chen, Jhih-Ci Chen, Meng-Ting Hsieh
  • Publication number: 20220043296
    Abstract: A display panel includes a substrate, a plurality of standard pixel units, and a plurality of dummy pixel units. A plurality of first conductor patterns and a plurality of shield blocks of a shield pattern layer are arranged in an array above the substrate. Each of the standard pixel units includes one of the first conductor patterns and a first shield block of the shield blocks. The first shield blocks and the first conductor patterns are overlapped, respectively. Each of the dummy pixel units includes a second shield block of the shield blocks. The second shield blocks and the first conductor patterns are not overlapped. A first edge of the substrate is spaced apart from a second edge of one of the standard pixel units adjacent to the dummy pixel units by a first distance. The first distance is within a range from 50 ?m to 3000 ?m.
    Type: Application
    Filed: October 20, 2021
    Publication date: February 10, 2022
    Applicant: Au Optronics Corporation
    Inventors: Ping-Hung Shih, Wei-Chieh Sun, Peng-Che Tai, Chia-Heng Chen, Jhih-Ci Chen, Meng-Ting Hsieh
  • Patent number: 11194188
    Abstract: A display panel includes a substrate, a plurality of standard pixel units, and a plurality of dummy pixel units. A plurality of first conductor patterns and a plurality of shield blocks of a shield pattern layer are arranged in an array above the substrate. Each of the standard pixel units includes one of the first conductor patterns and a first shield block of the shield blocks. The first shield blocks and the first conductor patterns are overlapped, respectively. Each of the dummy pixel units includes a second shield block of the shield blocks. The second shield blocks and the first conductor patterns are not overlapped. A first edge of the substrate is spaced apart from a second edge of one of the standard pixel units adjacent to the dummy pixel units by a first distance. The first distance is within a range from 50 ?m to 3000 ?m.
    Type: Grant
    Filed: November 10, 2019
    Date of Patent: December 7, 2021
    Assignee: Au Optronics Corporation
    Inventors: Ping-Hung Shih, Wei-Chieh Sun, Peng-Che Tai, Chia-Heng Chen, Jhih-Ci Chen, Meng-Ting Hsieh
  • Patent number: 11148519
    Abstract: A vehicle chassis including a vehicle frame defining an inner space and being operable to switch between a first expanded state and a collapsed state, and a loading device mounted to the inner space and removably connected to the vehicle frame. The loading device defines a first loading surface when the vehicle frame is in the first expanded state, and the loading device defines a second loading surface that is smaller than the first loading surface when the vehicle frame is in the collapsed state.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: October 19, 2021
    Assignee: NATIONAL TAIWAN NORMAL UNIVERSITY
    Inventors: Yi-Hsuan Hung, Ping-Hung Shih, Li-Fan Liu, Yi-Ya Liao, Kan-Yuan Tian
  • Patent number: 10971047
    Abstract: A device substrate including a substrate and 1st-stage to nth-stage driver units. Each of the 1st-stage to nth-stage driver units includes a pulldown element, a reset element, and an output element. A gate of the pulldown element is used for receiving a corresponding first start signal or a reset signal. A gate of the reset element is used for receiving the reset signal. A drain of the output element is used for outputting a corresponding gate driving signal. A gate of the pulldown element of the nth-stage driver unit is electrically connected with the gate of the reset element of the nth-stage driver unit so as to make the gate of the pulldown element of the nth-stage driver unit be used for receiving the reset signal.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: April 6, 2021
    Assignee: Au Optronics Corporation
    Inventors: Chia-Heng Chen, Yi-Fu Chen, Ping-Hung Shih, Wei-Chieh Sun, Peng-Che Tai, Jhih-Ci Chen
  • Publication number: 20210057453
    Abstract: A pixel array substrate, including gate elements and transfer elements, is provided. The gate elements include an n-th gate element and an m-th gate element. The transfer elements include a n-th transfer element and an m-th transfer element electrically connected to the n-th gate element and the m-th gate element respectively. A peripheral portion of each of the transfer elements includes a first straight section. A peripheral portion of the n-th transfer element further includes a first lateral section. The first lateral section of the n-th transfer element and the first straight section of the n-th transfer element respectively belong to a first conductive layer and a second conductive layer. A peripheral portion of the m-th transfer element crosses over the first lateral section of the peripheral portion of the n-th transfer element.
    Type: Application
    Filed: August 19, 2020
    Publication date: February 25, 2021
    Applicant: Au Optronics Corporation
    Inventors: Min-Tse Lee, Sheng-Yen Cheng, Yueh-Hung Chung, Ya-Ling Hsu, Chen-Hsien Liao, Peng-Che Tai, Ping-Hung Shih
  • Publication number: 20200410914
    Abstract: A device substrate including a substrate and 1st-stage to nth-stage driver units. Each of the 1st-stage to nth-stage driver units includes a pulldown element, a reset element, and an output element. A gate of the pulldown element is used for receiving a corresponding first start signal or a reset signal. A gate of the reset element is used for receiving the reset signal. A drain of the output element is used for outputting a corresponding gate driving signal. A gate of the pulldown element of the nth-stage driver unit is electrically connected with the gate of the reset element of the nth-stage driver unit so as to make the gate of the pulldown element of the nth-stage driver unit be used for receiving the reset signal.
    Type: Application
    Filed: October 8, 2019
    Publication date: December 31, 2020
    Applicant: Au Optronics Corporation
    Inventors: Chia-Heng Chen, Yi-Fu Chen, Ping-Hung Shih, Wei-Chieh Sun, Peng-Che Tai, Jhih-Ci Chen
  • Patent number: 10852608
    Abstract: A display panel includes an array substrate, a first pixel unit, a first data line, a common line, a first fanout line, and an opposite substrate. The array substrate includes a substrate including a first display region, a second display region, and a non-display region. The second display region includes a first side and a second side connected to the first side. The non-display region is adjacent connected to the first side. The first display region is adjacent connected to the second side. The first display region has a third side opposite to the second side. The third side is substantially aligned with an edge of the substrate. A first fanout line is disposed on the non-display region and connected to the first data line. The first fanout line has an end substantially aligned with the edge of the substrate.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: December 1, 2020
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Ping-Hung Shih, Meng-Ting Hsieh
  • Publication number: 20200363688
    Abstract: A display panel includes an array substrate, a first pixel unit, a first data line, a common line, a first fanout line, and an opposite substrate. The array substrate includes a substrate including a first display region, a second display region, and a non-display region. The second display region includes a first side and a second side connected to the first side. The non-display region is adjacent connected to the first side. The first display region is adjacent connected to the second side. The first display region has a third side opposite to the second side. The third side is substantially aligned with an edge of the substrate. A first fanout line is disposed on the non-display region and connected to the first data line. The first fanout line has an end substantially aligned with the edge of the substrate.
    Type: Application
    Filed: December 2, 2019
    Publication date: November 19, 2020
    Inventors: Ping-Hung SHIH, Meng-Ting HSIEH
  • Publication number: 20200239078
    Abstract: A vehicle chassis including a vehicle frame defining an inner space and being operable to switch between a first expanded state and a collapsed state, and a loading device mounted to the inner space and removably connected to the vehicle frame. The loading device defines a first loading surface when the vehicle frame is in the first expanded state, and the loading device defines a second loading surface that is smaller than the first loading surface when the vehicle frame is in the collapsed state.
    Type: Application
    Filed: November 13, 2019
    Publication date: July 30, 2020
    Applicant: National Taiwan Normal University
    Inventors: Yi-Hsuan HUNG, Ping-Hung SHIH, Li-Fan LIU, Yi-Ya LIAO, Kan-Yuan TIAN
  • Publication number: 20200166797
    Abstract: A display panel includes a substrate, a plurality of standard pixel units, and a plurality of dummy pixel units. A plurality of first conductor patterns and a plurality of shield blocks of a shield pattern layer are arranged in an array above the substrate. Each of the standard pixel units includes one of the first conductor patterns and a first shield block of the shield blocks. The first shield blocks and the first conductor patterns are overlapped, respectively. Each of the dummy pixel units includes a second shield block of the shield blocks. The second shield blocks and the first conductor patterns are not overlapped. A first edge of the substrate is spaced apart from a second edge of one of the standard pixel units adjacent to the dummy pixel units by a first distance. The first distance is within a range from 50 ?m to 3000 ?m.
    Type: Application
    Filed: November 10, 2019
    Publication date: May 28, 2020
    Applicant: Au Optronics Corporation
    Inventors: Ping-Hung Shih, Wei-Chieh Sun, Peng-Che Tai, Chia-Heng Chen, Jhih-Ci Chen, Meng-Ting Hsieh
  • Patent number: 10451935
    Abstract: An electronic device includes a substrate, a first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layer includes at least two first segments and at least one first connection line. The first connection line is connected to the at least two first segments. The second conductive layer includes at least two second segments and at least one second connection line. The at least two second segments do not overlap the at least two first segments in a normal direction of the substrate. The second connection line connects the at least two second segments. The second connection line overlaps the first connection line in the normal direction of the substrate. The third conductive layer includes at least one first connection electrode. The first connection electrode is electrically connected to the at least two first segments and the at least two second segments.
    Type: Grant
    Filed: April 28, 2019
    Date of Patent: October 22, 2019
    Assignee: Au Optronics Corporation
    Inventors: Kun-Lung Huang, Ping-Hung Shih
  • Publication number: 20190285929
    Abstract: An electronic device includes a substrate, a first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layer includes at least two first segments and at least one first connection line. The first connection line is connected to the at least two first segments. The second conductive layer includes at least two second segments and at least one second connection line. The at least two second segments do not overlap the at least two first segments in a normal direction of the substrate. The second connection line connects the at least two second segments. The second connection line overlaps the first connection line in the normal direction of the substrate. The third conductive layer includes at least one first connection electrode. The first connection electrode is electrically connected to the at least two first segments and the at least two second segments.
    Type: Application
    Filed: April 28, 2019
    Publication date: September 19, 2019
    Applicant: Au Optronics Corporation
    Inventors: Kun-Lung Huang, Ping-Hung Shih
  • Patent number: 10297619
    Abstract: An array substrate includes a substrate, first signal lines, sub-pixels, reference potential lines, first bonding pads, second bonding pads, first fan-out lines, second fan-out lines, first connection lines, second connection lines, and a first reference potential line. An accommodation space exists between a first connection line closest to the second bonding pads and a second connection line closest to the first bonding pads. The first reference potential line is disposed in the accommodation space and electrically connected with the reference potential lines.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: May 21, 2019
    Assignee: Au Optronics Corporation
    Inventors: Kun-Lung Huang, Ping-Hung Shih
  • Patent number: 10274795
    Abstract: An electronic device includes a substrate, a first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layer includes at least two first segments and at least one first connection line. The first connection line is connected to the at least two first segments. The second conductive layer includes at least two second segments and at least one second connection line. The at least two second segments do not overlap the at least two first segments in a normal direction of the substrate. The second connection line connects the at least two second segments. The second connection line overlaps the first connection line in the normal direction of the substrate. The third conductive layer includes at least one first connection electrode. The first connection electrode is electrically connected to the at least two first segments and the at least two second segments.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: April 30, 2019
    Assignee: Au Optronics Corporation
    Inventors: Kun-Lung Huang, Ping-Hung Shih
  • Publication number: 20190051668
    Abstract: An array substrate includes a substrate, first signal lines, sub-pixels, reference potential lines, first bonding pads, second bonding pads, first fan-out lines, second fan-out lines, first connection lines, second connection lines, and a first reference potential line. An accommodation space exists between a first connection line closest to the second bonding pads and a second connection line closest to the first bonding pads. The first reference potential line is disposed in the accommodation space and electrically connected with the reference potential lines.
    Type: Application
    Filed: December 21, 2017
    Publication date: February 14, 2019
    Applicant: Au Optronics Corporation
    Inventors: Kun-Lung Huang, Ping-Hung Shih
  • Publication number: 20070161134
    Abstract: A method of using nanoparticles to fabricate an emitting layer of an optical communication light source on a substrate is proposed, in which a host capable of reacting with unstable ions on the surface of a rare earth ions nanomaterial is used as a carrier of nanoparticles to make the rare earth ions nanomaterial release rare earth ions, thereby forming an emitting layer that can be excited by an external current or light source to emit light.
    Type: Application
    Filed: March 8, 2006
    Publication date: July 12, 2007
    Inventors: Ching-Fuh Lin, Kuo-Jui Sun, Ping-Hung Shih, Yi-Shin Su