Patents by Inventor Ping-Jung Yang

Ping-Jung Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200161245
    Abstract: A display device comprises a display panel substrate and a glass substrate over said display panel substrate, wherein said display panel substrate comprises multiple contact pads, a display area, a first boundary, a second boundary, a third boundary and a fourth boundary, wherein said display area comprises a first edge, a second edge, a third edge and a fourth edge, wherein said first boundary is parallel to said third boundary and said first and third edges, wherein said second boundary is parallel to said fourth boundary and said second and fourth edges, wherein a first least distance between said first boundary and said first edge, wherein a second least distance between said second boundary and said second edge, a third least distance between said third boundary and said third edge, a fourth distance between said fourth boundary and said fourth edge, and wherein said first, second, third and fourth least distances are smaller than 100 micrometers, and wherein said glass substrate comprising multiple meta
    Type: Application
    Filed: January 26, 2020
    Publication date: May 21, 2020
    Inventor: Ping-Jung Yang
  • Patent number: 10622310
    Abstract: A display device comprises a display panel substrate and a glass substrate over said display panel substrate, wherein said display panel substrate comprises multiple contact pads, a display area, a first boundary, a second boundary, a third boundary and a fourth boundary, wherein said display area comprises a first edge, a second edge, a third edge and a fourth edge, wherein said first boundary is parallel to said third boundary and said first and third edges, wherein said second boundary is parallel to said fourth boundary and said second and fourth edges, wherein a first least distance between said first boundary and said first edge, wherein a second least distance between said second boundary and said second edge, a third least distance between said third boundary and said third edge, a fourth distance between said fourth boundary and said fourth edge, and wherein said first, second, third and fourth least distances are smaller than 100 micrometers, and wherein said glass substrate comprising multiple meta
    Type: Grant
    Filed: September 11, 2016
    Date of Patent: April 14, 2020
    Inventor: Ping-Jung Yang
  • Patent number: 10453819
    Abstract: A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors has a third surface and a fourth surface, wherein the third surface and the first surface are substantially coplanar, wherein the second surface and the fourth surface are substantially coplanar, wherein one of the conductors comprise a copper-tungsten alloy material, wherein the solid glass core is directly contact with the conductor; and a first dielectric layer and a first metal layer formed at the first surface, wherein the first metal layer at the first surface is electrically coupled with one of the conductors.
    Type: Grant
    Filed: September 23, 2018
    Date of Patent: October 22, 2019
    Inventor: Ping-Jung Yang
  • Publication number: 20190027459
    Abstract: A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors has a third surface and a fourth surface, wherein the third surface and the first surface are substantially coplanar, wherein the second surface and the fourth surface are substantially coplanar, wherein one of the conductors comprise a copper-tungsten alloy material, wherein the solid glass core is directly contact with the conductor; and a first dielectric layer and a first metal layer formed at the first surface, wherein the first metal layer at the first surface is electrically coupled with one of the conductors.
    Type: Application
    Filed: September 23, 2018
    Publication date: January 24, 2019
    Inventor: Ping-Jung Yang
  • Patent number: 10096565
    Abstract: A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors has a third surface and a fourth surface, wherein the third surface and the first surface are substantially coplanar, wherein the second surface and the fourth surface are substantially coplanar, wherein one of the conductors comprise a copper-tungsten alloy material, wherein the solid glass core is directly contact with the conductor; and a first dielectric layer and a first metal layer formed at the first surface, wherein the first metal layer at the first surface is electrically coupled with one of the conductors.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: October 9, 2018
    Inventor: Ping-Jung Yang
  • Publication number: 20170207188
    Abstract: A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors has a third surface and a fourth surface, wherein the third surface and the first surface are substantially coplanar, wherein the second surface and the fourth surface are substantially coplanar, wherein one of the conductors comprise a copper-tungsten alloy material, wherein the solid glass core is directly contact with the conductor; and a first dielectric layer and a first metal layer formed at the first surface, wherein the first metal layer at the first surface is electrically coupled with one of the conductors.
    Type: Application
    Filed: April 1, 2017
    Publication date: July 20, 2017
    Inventor: Ping-Jung Yang
  • Patent number: 9615453
    Abstract: A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors has a third surface and a fourth surface, wherein the third surface and the first surface are substantially coplanar, wherein the second surface and the fourth surface are substantially coplanar, wherein one of the conductors comprise a copper-tungsten alloy material, wherein the solid glass core is directly contact with the conductor; and a first dielectric layer and a first metal layer formed at the first surface, wherein the first metal layer at the first surface is electrically coupled with one of the conductors.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: April 4, 2017
    Inventor: Ping-Jung Yang
  • Patent number: 9612615
    Abstract: Integrated circuit chips and chip packages are disclosed that include an over-passivation scheme at a top of the integrated circuit chip and a bottom scheme at a bottom of the integrated circuit chip using a top post-passivation technology and a bottom structure technology. The integrated circuit chips can be connected to an external circuit or structure, such as ball-grid-array (BGA) substrate, printed circuit board, semiconductor chip, metal substrate, glass substrate or ceramic substrate, through the over-passivation scheme or the bottom scheme. Related fabrication techniques are described.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: April 4, 2017
    Assignee: QUALCOMM INCORPORATED
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee, Hsin-Jung Lo, Ping-Jung Yang, Te-Sheng Liu
  • Publication number: 20170047313
    Abstract: A display device comprises a display panel substrate and a glass substrate over said display panel substrate, wherein said display panel substrate comprises multiple contact pads, a display area, a first boundary, a second boundary, a third boundary and a fourth boundary, wherein said display area comprises a first edge, a second edge, a third edge and a fourth edge, wherein said first boundary is parallel to said third boundary and said first and third edges, wherein said second boundary is parallel to said fourth boundary and said second and fourth edges, wherein a first least distance between said first boundary and said first edge, wherein a second least distance between said second boundary and said second edge, a third least distance between said third boundary and said third edge, a fourth distance between said fourth boundary and said fourth edge, and wherein said first, second, third and fourth least distances are smaller than 100 micrometers, and wherein said glass substrate comprising multiple meta
    Type: Application
    Filed: September 11, 2016
    Publication date: February 16, 2017
    Inventor: Ping-Jung Yang
  • Patent number: 8837872
    Abstract: A device is described which includes a waveguide structure for signal transmission and power/ground delivery The waveguide structure includes a signal transmission part for transmitting an optical signal from an illuminant device to a detector. The signal transmission part may include transparent polymer, diamond or glass. The signal transmission part is used for a waveguide. The waveguide structure further includes a power/ground delivery part surrounding the signal transmission part. The power/ground delivery part is composed of at least one metal layer. Thus, the waveguide structure can provide an optical-signal transmission with high speed and high volume through the signal transmission part, while a stable power or ground reference can be provided to multiple units through the power/ground delivery part.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: September 16, 2014
    Assignee: Qualcomm Incorporated
    Inventors: Ping-Jung Yang, Hsin-Jung Lo, Te-Sheng Liu
  • Publication number: 20140085842
    Abstract: A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors has a third surface and a fourth surface, wherein the third surface and the first surface are substantially coplanar, wherein the second surface and the fourth surface are substantially coplanar, wherein one of the conductors comprise a copper-tungsten alloy material, wherein the solid glass core is directly contact with the conductor; and a first dielectric layer and a first metal layer formed at the first surface, wherein the first metal layer at the first surface is electrically coupled with one of the conductors.
    Type: Application
    Filed: September 25, 2013
    Publication date: March 27, 2014
    Inventor: Ping-Jung Yang
  • Publication number: 20130242500
    Abstract: Integrated circuit chips and chip packages are disclosed that include an over-passivation scheme at a top of the integrated circuit chip and a bottom scheme at a bottom of the integrated circuit chip using a top post-passivation technology and a bottom structure technology. The integrated circuit chips can be connected to an external circuit or structure, such as ball-grid-array (BGA) substrate, printed circuit board, semiconductor chip, metal substrate, glass substrate or ceramic substrate, through the over-passivation scheme or the bottom scheme. Related fabrication techniques are described.
    Type: Application
    Filed: May 1, 2013
    Publication date: September 19, 2013
    Applicant: Megica Corporation
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee, Hsin-Jung Lo, Ping-Jung Yang, Te-Sheng Liu
  • Patent number: 8456856
    Abstract: Integrated circuit chips and chip packages are disclosed that include an over-passivation scheme at a top of the integrated circuit chip and a bottom scheme at a bottom of the integrated circuit chip using a top post-passivation technology and a bottom structure technology. The integrated circuit chips can be connected to an external circuit or structure, such as ball-grid-array (BGA) substrate, printed circuit board, semiconductor chip, metal substrate, glass substrate or ceramic substrate, through the over-passivation scheme or the bottom scheme. Related fabrication techniques are described.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: June 4, 2013
    Assignee: Megica Corporation
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee, Hsin-Jung Lo, Ping-Jung Yang, Te-Sheng Liu
  • Patent number: 8431977
    Abstract: A semiconductor chip includes a silicon substrate, a transistor in or on a bottom side surface of the substrate, a metallization structure under a bottom side surface of the substrate, a dielectric layer under the substrate and between a first and second metal layers of the metallization structure, a passivation layer under the metallization structure and the dielectric layer, where an opening in the passivation layer may be under a contact point of the metallization structure, a polymer layer under the passivation layer, a metal post under the passivation layer and in the polymer layer, where the polymer layer may not cover a bottom surface of the metal post, a metal bump connected with the bottom surface of the metal post, a micro-lense over the top side surface of the substrate, and a glass substrate over the micro-lense and over the top side surface of the substrate.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: April 30, 2013
    Assignee: Megica Corporation
    Inventor: Ping-Jung Yang
  • Publication number: 20120193785
    Abstract: Multichip packages or multichip modules may include stacked chips and through silicon/substrate vias (TSVs) formed using enclosure-first technology. Enclosure-first technology may include forming an isolation enclosure associated with a TSV early in the fabrication process, without actually forming the associated TSV. The TSV associated with the isolation enclosure is formed later in the fabrication process. The enclosure-first technology allows the isolation enclosures to be used as alignment marks for stacking additional chips. The stacked chips can be connected to each other or to an external circuit such that data input is provided through the bottom-most (or topmost) chip, data is output from the bottom-most (or topmost) chip. The multichip package may provide a serial data connection, and a parallel connection, to each of the stacked chips.
    Type: Application
    Filed: January 25, 2012
    Publication date: August 2, 2012
    Applicant: Megica Corporation
    Inventors: Mou-Shiung Lin, Ping-Jung Yang, Hsin-Jung Lo, Te-Sheng Liu, Jin-Yuan Lee
  • Publication number: 20120170887
    Abstract: A device is described which includes a waveguide structure for signal transmission and power/ground delivery The waveguide structure includes a signal transmission part for transmitting an optical signal from an illuminant device to a detector. The signal transmission part may include transparent polymer, diamond or glass. The signal transmission part is used for a waveguide. The waveguide structure further includes a power/ground delivery part surrounding the signal transmission part. The power/ground delivery part is composed of at least one metal layer. Thus, the waveguide structure can provide an optical-signal transmission with high speed and high volume through the signal transmission part, while a stable power or ground reference can be provided to multiple units through the power/ground delivery part.
    Type: Application
    Filed: December 27, 2011
    Publication date: July 5, 2012
    Applicant: MEGICA CORPORATION
    Inventors: Ping-Jung Yang, Hsin-Jung Lo, Te-Sheng Liu
  • Publication number: 20110304008
    Abstract: A semiconductor chip includes a silicon substrate, a transistor in or on a bottom side surface of the substrate, a metallization structure under a bottom side surface of the substrate, a dielectric layer under the substrate and between a first and second metal layers of the metallization structure, a passivation layer under the metallization structure and the dielectric layer, where an opening in the passivation layer may be under a contact point of the metallization structure, a polymer layer under the passivation layer, a metal post under the passivation layer and in the polymer layer, where the polymer layer may not cover a bottom surface of the metal post, a metal bump connected with the bottom surface of the metal post, a micro-lense over the top side surface of the substrate, and a glass substrate over the micro-lense and over the top side surface of the substrate.
    Type: Application
    Filed: June 10, 2011
    Publication date: December 15, 2011
    Applicant: Magica Corporation
    Inventor: Ping-Jung Yang
  • Publication number: 20100246152
    Abstract: Integrated circuit chips and chip packages are disclosed that include an over-passivation scheme at a top of the integrated circuit chip and a bottom scheme at a bottom of the integrated circuit chip using a top post-passivation technology and a bottom structure technology. The integrated circuit chips can be connected to an external circuit or structure, such as ball-grid-array (BGA) substrate, printed circuit board, semiconductor chip, metal substrate, glass substrate or ceramic substrate, through the over-passivation scheme or the bottom scheme. Related fabrication techniques are described.
    Type: Application
    Filed: March 11, 2010
    Publication date: September 30, 2010
    Applicant: Megica Corporation
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee, Hsin-Jung Lo, Ping-Jung Yang, Te-Sheng Liu