Patents by Inventor Ping-Kun Wu
Ping-Kun Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7737556Abstract: An integrated circuit device comprising a partially embedded and encapsulated damascene structure and method for forming the same to improve adhesion to an overlying dielectric layer, the integrated circuit device including a conductive material partially embedded in an opening formed in a dielectric layer; wherein said conductive material is encapsulated with a first barrier layer comprising sidewall and bottom portions and a second barrier layer covering a top portion, said conductive material and first barrier layer sidewall portions extending to a predetermined height above an upper surface of the dielectric layer to form a partially embedded damascene.Type: GrantFiled: September 30, 2005Date of Patent: June 15, 2010Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Chao-Hsiung Wang, Ping-Kun Wu
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Patent number: 7381649Abstract: A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.Type: GrantFiled: July 29, 2005Date of Patent: June 3, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Wei Chen, Tang-Xuan Zhong, Sheng-Da Liu, Chang-Yun Chang, Ping-Kun Wu, Chao-Hsiung Wang, Fu-Liang Yang
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Patent number: 7265038Abstract: A copper filled damascene structure and method for forming the same the method including providing a substrate comprising a semiconductor substrate; forming an insulator layer on the substrate; forming a damascene opening through a thickness portion of the insulator layer; forming a diffusion barrier layer to line the damascene opening; forming a first seed layer overlying the diffusion barrier; plasma treating the first seed layer in-situ with a first treatment plasma comprising plasma source gases selected from the group consisting of argon, nitrogen, hydrogen, and NH3; forming a second seed layer overlying the first seed layer; forming a copper layer overlying the second seed layer according to an electro-chemical plating (ECP) process to fill the damascene opening; and, planarizing the copper layer to form a metal interconnect structure.Type: GrantFiled: November 25, 2003Date of Patent: September 4, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ping-Kun Wu, Horng-Huei Tseng, Chine-Gie Lo, Chao-Hsiung Wang, Shau-Lin Shue
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Patent number: 7208815Abstract: In preferred embodiments of the present invention, a method of forming CMOS devices using SOI and hybrid substrate orientations is described. In accordance with a preferred embodiment, a substrate may have multiple crystal orientations. One logic gate in the substrate may comprise at least one N-FET on one crystal orientation and at least one P-FET on another crystal orientation. Another logic gate in the substrate may comprise at least one N-FET and at least one P-FET on the same orientation. Alternative embodiments further include determining the preferred cleavage planes of the substrates and orienting the substrates relative to each other in view of their respective preferred cleavage planes. In a preferred embodiment, the cleavage planes are not parallel.Type: GrantFiled: November 15, 2004Date of Patent: April 24, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Wei Chen, Ping-Kun Wu, Chao-Hsiung Wang, Fu-Liang Yang, Chenming Hu
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Publication number: 20070075428Abstract: An integrated circuit device comprising a partially embedded and encapsulated damascene structure and method for forming the same to improve adhesion to an overlying dielectric layer, the integrated circuit device including a conductive material partially embedded in an opening formed in a dielectric layer; wherein said conductive material is encapsulated with a first barrier layer comprising sidewall and bottom portions and a second barrier layer covering a top portion, said conductive material and first barrier layer sidewall portions extending to a predetermined height above an upper surface of the dielectric layer to form a partially embedded damascene.Type: ApplicationFiled: September 30, 2005Publication date: April 5, 2007Inventors: Chao-Hsiung Wang, Ping-Kun Wu
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Patent number: 7105897Abstract: This invention discloses a method and a semiconductor structure for integrating at least one bulk device and at least one silicon-on-insulator (SOI) device. The semiconductor structure includes a first substrate having an SOI area and a bulk area, on which the bulk device is formed; an insulation layer formed on the first substrate in the SOI area; and a second substrate, on which the SOI device is formed, stacked on the insulation layer. The surface of the first substrate is not on the substantially same plane as the surface of the second substrate.Type: GrantFiled: October 28, 2004Date of Patent: September 12, 2006Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Hao-Yu Chen, Fu-Liang Yang, Hung-Wei Chen, Ping-Kun Wu, Chao-Hsiung Wang
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Publication number: 20060097316Abstract: This invention discloses a method and a semiconductor structure for integrating at least one bulk device and at least one silicon-on-insulator (SOI) device. The semiconductor structure includes a first substrate having an SOI area and a bulk area, on which the bulk device is formed; an insulation layer formed on the first substrate in the SOI area; and a second substrate, on which the SOI device is formed, stacked on the insulation layer. The surface of the first substrate is not on the substantially same plane as the surface of the second substrate.Type: ApplicationFiled: October 28, 2004Publication date: May 11, 2006Inventors: Hao-Yu Chen, Fu-Liang Yang, Hung-Wei Chen, Ping-Kun Wu, Chao-Hsiung Wang
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Publication number: 20060049460Abstract: In preferred embodiments of the present invention, a method of forming CMOS devices using SOI and hybrid substrate orientations is described. In accordance with a preferred embodiment, a substrate may have multiple crystal orientations. One logic gate in the substrate may comprise at least one N-FET on one crystal orientation and at least one P-FET on another crystal orientation. Another logic gate in the substrate may comprise at least one N-FET and at least one P-FET on the same orientation. Alternative embodiments further include determining the preferred cleavage planes of the substrates and orienting the substrates relative to each other in view of their respective preferred cleavage planes. In a preferred embodiment, the cleavage planes are not parallel.Type: ApplicationFiled: November 15, 2004Publication date: March 9, 2006Inventors: Hung-Wei Chen, Ping-Kun Wu, Chao-Hsiung Wang, Fu-Liang Yang, Chenming Hu
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Publication number: 20050263891Abstract: A damascene structure for semiconductor devices is provided. In an embodiment, the damascene structure includes trenches formed over vias that electrically couple the trenches to an underlying conductive layer such that the trenches have varying widths. The vias are lined with a first barrier layer. The first barrier layers along the bottom of vias are removed such that a recess formed in the underlying conductive layer. The recesses formed along the bottom of vias are such that the recess below narrower trenches is greater than the recess formed below wider trenches. In another embodiment, a second barrier layer may then be formed over the first barrier layer. In this embodiment, a portion of the conductive layer may be interposed between the first barrier layer and the second barrier layer.Type: ApplicationFiled: April 7, 2005Publication date: December 1, 2005Inventors: Bih-Huey Lee, Hong-Yuan Chu, Ping-Kun Wu, Ching-Wen Lu, Jing-Cheng Lin, Shau-Lin Shue, Shing-Chyang Pan
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Publication number: 20050110147Abstract: A copper filled damascene structure and method for forming the same the method including providing a substrate comprising a semiconductor substrate; forming an insulator layer on the substrate; forming a damascene opening through a thickness portion of the insulator layer; forming a diffusion barrier layer to line the damascene opening; forming a first seed layer overlying the diffusion barrier; plasma treating the first seed layer in-situ with a first treatment plasma comprising plasma source gases selected from the group consisting of argon, nitrogen, hydrogen, and NH3; forming a second seed layer overlying the first seed layer; forming a copper layer overlying the second seed layer according to an electro-chemical plating (ECP) process to fill the damascene opening; and, planarizing the copper layer to form a metal interconnect structure.Type: ApplicationFiled: November 25, 2003Publication date: May 26, 2005Inventors: Ping-Kun Wu, Horng-Huei Tseng, Chine-Gie Lo, Chao-Hsiung Wang, Shau-Lin Shue
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Publication number: 20030071755Abstract: A helix antenna with a cap of high dielectric coefficient, which includes the cap to be installed on the end portion of an insulating sleeve, a coil is positioned in the cap and the insulating sleeve. The cap is made of high dielectric coefficient material with an internal extension post integrally shaped therein in matching with the coil by diameter in order that the coil is fitted over the internal extension post, a high dielectric coefficient thus is obtained inside the coil to thereby decrease wavelength correspondingly. Verticality of the coil can be corrected to improve electric stability and make the overall length of the helix antenna be shortened effectively. Thus an improved helix antenna can be formed.Type: ApplicationFiled: October 12, 2001Publication date: April 17, 2003Applicant: Auden Techno Corp.Inventors: Jammy Lin, Ping Kun Wu
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Patent number: 6483479Abstract: An instantly welded antenna of which a helical coil is positioned on an end face of a metallic seat member thereof; the metallic seat member and the helical coil are put into a matched inner blind hole of a plastic insulating sleeve. A heated surface provided on the metallic seat member can be heated instantly. The peripheral surface of the metallic seat member and the inside surface of the matched inner blind hole of the insulating sleeve is used as a heat conductive welding surface to weld the metallic seat member and the insulating sleeve, and the helical coil is positioned therein. Thus, the core diameter, the pitch and the overall length of the helix coil can be maintained, not only the inferiority of products is lowered, but also the processing efficiency of the products is increased.Type: GrantFiled: August 29, 2001Date of Patent: November 19, 2002Assignee: Auden Techno Corp.Inventors: Jammy Lin, Ping Kun Wu
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Patent number: RE45165Abstract: A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.Type: GrantFiled: February 14, 2012Date of Patent: September 30, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Wei Chen, Tang-Xuan Zhong, Sheng-Da Liu, Chang-Yu Chang, Ping-Kun Wu, Chao-Hsiung Wang, Fu-Liang Yang
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Patent number: RE45180Abstract: A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.Type: GrantFiled: June 2, 2010Date of Patent: October 7, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Wei Chen, Tang-Xuan Zhong, Sheng-Da Liu, Chang-Yun Chang, Ping-Kun Wu, Chao-Hsiung Wang, Fu-Liang Yang
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Patent number: RE45944Abstract: A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.Type: GrantFiled: August 22, 2014Date of Patent: March 22, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Wei Chen, Tang-Xuang Zhong, Sheng-Da Liu, Chang-Yun Chang, Ping-Kun Wu, Chao-Hsiung Wang, Fu-Liang Yang