Abstract: A semiconductor device according to the present disclosure includes a memory array having a plurality of memory cells arranged in a row, and an interconnect structure disposed over the memory cells and having a bit line coupled to each of the memory cells arranged in the row. The bit line has a first segment coupled to a first portion of the memory cells and a second segment coupled to a second portion of the memory cells. The first segment has a first width and the second segment has a second width that is smaller than the first width.

Abstract: Semiconductor structures and methods are provided. An exemplary semiconductor structure according to the present disclosure includes a two-port static random access memory (SRAM) cell having a write port portion and a read port portion electrically coupled to the write port portion. The read port portion includes a transistor having a first source/drain feature and a second source/drain feature. The semiconductor structure also includes a first plurality of metal lines comprising a write bit line and a complementary write bit line, wherein the first plurality of metal lines are positioned at a first metal interconnect layer, wherein the first metal interconnect layer is disposed over the first source/drain feature. The semiconductor structure also includes a read bit line positioned at a second metal interconnect layer, where the second metal interconnect layer is disposed under the first source/drain feature.

Abstract: An integrated circuit includes a first SRAM cell and a second SRAM cell, each including a plurality of field-effect transistors (FETs), a front metal line over the FETs and a back metal line below the FETs, and a middle strap area disposed between the first SRAM cell and the second SRAM cell. The middle strap area includes a plurality of gate stacks extending lengthwise along a direction, a gate isolation structure extending through a gate stack of the plurality of gate stacks, a feedthrough via (FTV) embedded in the gate isolation structure, a first dielectric gate disposed between the conductive structure and the first SRAM cell, and a second dielectric gate disposed between the conductive structure and the second SRAM cell. The FTV electrically couples the front metal line and the back metal line.

Abstract: Semiconductor structures and methods are provided. An exemplary semiconductor structure according to the present disclosure includes a two-port static random access memory (SRAM) cell having a write port portion and a read port portion electrically coupled to the write port portion. The read port portion includes a transistor having a gate structure. The semiconductor structure also includes a first plurality of metal lines comprising a write bit line and a complementary write bit line are positioned at a first interconnect layer disposed over the gate structure and a read word line positioned at a second interconnect layer and electrically coupled to the gate structure, the second interconnect layer is disposed under the gate structure.

Abstract: An electronic package module and a method for fabrication of the same are provided. The method includes providing an electronic component assembly and a circuit substrate. The electronic component assembly includes two electronic components and a conductive structure. The electronic components are connected to each other through a conductive adhesive material, while the electronic components are connected to the conductive structure through another conductive adhesive material. A soldering material is formed on the circuit substrate, and the electronic component assembly is disposed on the soldering material. The melting points of the conductive adhesive materials are higher than the melting point of the soldering material. As a result, the conductive adhesive materials are prevented from failure during the soldering process, and thus the process yield is improved.

Abstract: A semiconductor structure includes a first source/drain (S/D) epitaxial feature, a second S/D epitaxial feature adjacent to the first S/D epitaxial feature, an insulating structure between the first and the second S/D epitaxial features, and a shared S/D contact over top surfaces of the first and the second S/D epitaxial features. A center portion of the shared S/D contact is directly between a side surface of the first S/D epitaxial feature and a side surface of the second S/D epitaxial feature. The center portion is directly above the insulating structure. The semiconductor structure further includes a backside via penetrating through the insulating structure to directly land on a bottom surface of the center portion.

Abstract: A circuit board assembly in a camera module for blocking unwanted light when images are captured includes a circuit board, a sensor, and an optical blocking body connecting the circuit board and the sensor. The circuit board includes a base board and a photomask. The photomask is arranged on a surface of the base board, the base board includes conductive circuit layers and dielectric layers, the conductive circuit layers and the dielectric layers are alternately arranged, the sensor being electronically connected to the conductive layers. The optical blocking body, the photomask, and the dielectric layers block ambient light entering the camera module other than through the lens assembly of the camera module.

Abstract: The present disclosure provides an integrated circuit (IC) structure that includes a semiconductor substrate having a frontside and a backside; a shallow trench isolation (STI) structure formed in the semiconductor substrate and defining an active region, wherein the STI structure includes a STI bottom surface, wherein the semiconductor substrate includes a substrate bottom surface, and wherein the STI bottom surface and the substrate bottom surface are coplanar; a field-effect transistor (FET) over the active region and formed on the frontside of the semiconductor substrate; and a backside dielectric layer disposed on the substrate bottom surface and the STI bottom surface.

Abstract: The present disclosure provides embodiments of electronic fuse devices. An electronic fuse device according to the present disclosure includes a first bit cell comprising a first plurality of active regions extending along a first direction and a second bit cell comprising a second plurality of active regions extending along the first direction. Each of the first plurality of active regions is aligned with one of the second plurality of active regions along the first direction. The first bit cell and the second bit cell are spaced apart along the first direction by a space and the space is free of a well tap cell.

Abstract: The present disclosure provides an IC structure that includes a semiconductor substrate having a SRAM region, an input/output and peripheral (IOP) region, and an edge region spanning tween the SRAM region and the IOP region; a STI structure formed on the semiconductor substrate and defining active regions; a SRAM cell formed within the SRAM region; and a backside dielectric layer disposed on a backside of the semiconductor substrate and landing on a bottom surface of the STI structure. The active regions are longitudinally oriented along a first direction; gates are formed on the semiconductor substrate and are evenly distributed with a pitch P along the first direction; the SRAM cell spans a first dimension Ds along the first direction; the edge region spans a second dimension De along the first direction; and a ratio De/Ds equals to 2 or is less than 2.

Abstract: An integrated circuit (IC) device has a memory region in which a plurality of memory cells is implemented. Each of the memory cells has a first dimension in a first horizontal direction. The IC device includes an edge region bordering the memory cell region in the first horizontal direction. The edge region has a second dimension in the first horizontal direction. The second dimension is less than or equal to about 4 times the first dimension. The IC device is formed by revising a first IC layout to generate a second IC layout. The second IC layout is generated by shrinking a dimension of the edge region in the first horizontal direction.

Abstract: A shift register is disclosed herein. The shift register includes a pull down circuit, a supplementary circuit, an output control circuit, and an input circuit. The supplementary circuit is coupled to the pull down circuit at a first node and a second node and is configured to receive a touch signal. The output control circuit is coupled to the second node. The input circuit is coupled to the first node and is configured to transmit an input voltage to the first node and the second node according to an input signal. The supplementary circuit transmits a voltage value of the touch signal to the second node according to the input voltage and the touch signal, so as to maintain a voltage value of the second node.

Abstract: A display device comprises a plurality of pixels and a plurality of multiplexers. Each of the plurality of multiplexers is coupled with N data lines, and configured to receive N?1 switching signals and a data signal. N is a positive integer larger than or equal to 3, and each of the N data lines is coupled with one column of pixels of the plurality of pixels. When any of the N?1 switching signals has an enabling voltage level, the multiplexer is disabled from transmitting the data signal to an N-th data line of the N data lines. When each of the N?1 switching signals has a disabling voltage level, the multiplexer transmits the data signal to the N-th data line.

Abstract: A method for driving the multiplexer is disclosed herein. The method includes the following operations: in a first frame, a first control signal is configured to enable a partial of switch of a first multiplexer and a partial of switch of a second multiplexer; and in a second frame, a second control signal is configured to enable another partial of switch of the first multiplexer and another partial of switch of the second multiplexer.

Abstract: A method for driving the multiplexer is disclosed herein. The method includes the following operations: in a first frame, a first control signal is configured to enable a partial of switch of a first multiplexer and a partial of switch of a second multiplexer; and in a second frame, a second control signal is configured to enable another partial of switch of the first multiplexer and another partial of switch of the second multiplexer.

Abstract: A display device comprises a plurality of pixels and a plurality of multiplexers. Each of the plurality of multiplexers is coupled with N data lines, and configured to receive N?1 switching signals and a data signal. N is a positive integer larger than or equal to 3, and each of the N data lines is coupled with one column of pixels of the plurality of pixels. When any of the N?1 switching signals has an enabling voltage level, the multiplexer is disabled from transmitting the data signal to an N-th data line of the N data lines. When each of the N?1 switching signals has a disabling voltage level, the multiplexer transmits the data signal to the N-th data line.

Abstract: A shift register is disclosed herein. The shift register includes a pull down circuit, a supplementary circuit, an output control circuit, and an input circuit. The supplementary circuit is coupled to the pull down circuit at a first node and a second node and is configured to receive a touch signal. The output control circuit is coupled to the second node. The input circuit is coupled to the first node and is configured to transmit an input voltage to the first node and the second node according to an input signal. The supplementary circuit transmits a voltage value of the touch signal to the second node according to the input voltage and the touch signal, so as to maintain a voltage value of the second node.

Abstract: A multiplexer circuit and a display panel thereof are provided. The multiplexer circuit includes a first switch, a second switch, and a pull-down circuit. The first switch has a first terminal coupled to a first source line, a control terminal receiving a first switching signal, and a second terminal coupled to a source driver. The second switch has a first terminal coupled to a second source line, a control terminal receiving a second switching signal, and a second terminal coupled to the source driver. The pull-down circuit is coupled to the control terminal of the first switch and receives a system low voltage. The pull-down circuit transmits the system low voltage to the control terminal of the first switch during a rising edge of the second switching signal to turn off the first switch before the second switch is turned on.

Abstract: A touch panel includes a first gate drive circuit, a first touch circuit, a second gate drive circuit, and a second touch circuit. The first touch circuit is connected to the first gate drive circuit and includes a first capacitor. The second touch circuit is connected to the second gate drive circuit and includes a second capacitor. The first capacitor and the second capacitor are connected in parallel.

Abstract: A multiplexer circuit and a display panel thereof are provided. The multiplexer circuit includes a first switch, a second switch, and a pull-down circuit. The first switch has a first terminal coupled to a first source line, a control terminal receiving a first switching signal, and a second terminal coupled to a source driver. The second switch has a first terminal coupled to a second source line, a control terminal receiving a second switching signal, and a second terminal coupled to the source driver. The pull-down circuit is coupled to the control terminal of the first switch and receives a system low voltage. The pull-down circuit transmits the system low voltage to the control terminal of the first switch during a rising edge of the second switching signal to turn off the first switch before the second switch is turned on.