Patents by Inventor Ping Lin
Ping Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11968910Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, forming an etch stop layer on the MTJ stack, forming a first spin orbit torque (SOT) layer on the etch stop layer, and then patterning the first SOT layer, the etch stop layer, and the MTJ stack to form a MTJ.Type: GrantFiled: October 14, 2021Date of Patent: April 23, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hung-Chan Lin, Yu-Ping Wang, Chien-Ting Lin
-
Patent number: 11967279Abstract: Provided are a pixel driving circuit, a method for driving the pixel driving circuit, a silicon-based display panel and a display device. The pixel driving circuit is used for driving a light-emitting element to emit light. At an initial stage, a reset circuit provides a reset signal to a third node; a light emission control transistor is in a first on state to transmit the reset signal to a second node; a threshold compensation circuit transmits the reset signal to a first node; and a data write circuit transmits a non-enable level Vofs of a data signal to a second terminal of a first capacitor. At a threshold compensation stage, the threshold compensation circuit provides a threshold voltage of a drive transistor to the first node for compensation.Type: GrantFiled: July 15, 2022Date of Patent: April 23, 2024Assignee: SEEYA OPTRONICS CO., LTD.Inventors: Ping-lin Liu, Tong Wu
-
Patent number: 11968911Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a first spin orbit torque (SOT) layer on the MTJ stack; forming a first hard mask on the first SOT layer; and using a second hard mask to pattern the first hard mask, the first SOT layer, and the MTJ stack to form a MTJ.Type: GrantFiled: November 3, 2021Date of Patent: April 23, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hung-Chan Lin, Yu-Ping Wang, Chien-Ting Lin
-
Patent number: 11967898Abstract: A soft-switching power converter includes a main switch, an energy-releasing switch, and an inductive coupled unit. The main switch is a controllable switch. The energy-releasing switch is coupled to the main switch. The inductive coupled unit is coupled to the main switch and the energy-releasing switch. The inductive coupled unit includes a first inductance, a second inductance coupled to the first inductance, and an auxiliary switch unit. The auxiliary switch unit is coupled to the second inductance to form a closed loop. The main switch and the energy-releasing switch are alternately turned on and turned off. The auxiliary switch unit is controlled to start turning on before the main switch is turned on so as to provide at least one current path.Type: GrantFiled: January 6, 2022Date of Patent: April 23, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Hung-Chieh Lin, Yi-Ping Hsieh, Jin-Zhong Huang, Hung-Yu Huang, Chih-Hsien Li, Ciao-Yin Pan
-
Patent number: 11968817Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.Type: GrantFiled: February 28, 2022Date of Patent: April 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jui-Lin Chen, Chao-Yuan Chang, Ping-Wei Wang, Fu-Kai Yang, Ting Fang, I-Wen Wu, Shih-Hao Lin
-
Patent number: 11963348Abstract: A method of making a ROM structure includes the operations of forming an active area having a channel, a source region, and a drain region; depositing a gate electrode over the channel; depositing a conductive line over at least one of the source region and the drain region; adding dopants to the source region and the drain region of the active area; forming contacts to the gate electrode, the source region, and the drain; depositing a power rail, a bit line, and at least one word line of the integrated circuit against the contacts; and dividing the active area with a trench isolation structure to electrically isolate the gate electrode from the source region and the drain region.Type: GrantFiled: August 10, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Geng-Cing Lin, Ze-Sian Lu, Meng-Sheng Chang, Chia-En Huang, Jung-Ping Yang, Yen-Huei Chen
-
Patent number: 11955370Abstract: A system and methods of forming a dielectric material within a trench are described herein. In an embodiment of the method, the method includes introducing a first precursor into a trench of a dielectric layer, such that portions of the first precursor react with the dielectric layer and attach on sidewalls of the trench. The method further includes partially etching portions of the first precursor on the sidewalls of the trench to expose upper portions of the sidewalls of the trench. The method further includes introducing a second precursor into the trench, such that portions of the second precursor react with the remaining portions of the first precursor to form the dielectric material at the bottom of the trench.Type: GrantFiled: September 18, 2020Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Bo-Cyuan Lu, Ting-Gang Chen, Sung-En Lin, Chunyao Wang, Yung-Cheng Lu, Chi On Chui, Tai-Chun Huang, Chieh-Ping Wang
-
Patent number: 11955385Abstract: A semiconductor device includes a first stack structure, a second stack structure, and a third stack structure. Each of the stack structure includes semiconductor layers vertically spaced from one another. The first, second, and third stack structures all extend along a first lateral direction. The second stack structure is disposed between the first and third stack structures. The semiconductor device includes a first gate structure that extends along a second lateral direction and wraps around each of the semiconductor layers. The semiconductor layers of the first stack structure are coupled with respective source/drain structures. The semiconductor layers of the second stack structure are coupled with respective source/drain structures. The semiconductor layers of the third stack structure are coupled with a dielectric passivation layer.Type: GrantFiled: August 27, 2021Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Chih-Han Lin, Chen-Ping Chen, Hsiao Wen Lee
-
Patent number: 11956973Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first spin orbit torque (SOT) layer on the MTJ; forming a passivation layer around the MTJ; forming a second SOT layer on the first SOT layer and the passivation layer; and patterning the second SOT layer and the passivation layer.Type: GrantFiled: July 7, 2021Date of Patent: April 9, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hung-Chan Lin, Yu-Ping Wang
-
Publication number: 20240111453Abstract: A memory device and a management method thereof are provided. The memory device includes a controller and at least one memory channel. The memory channel includes at least one memory chip. The at least one memory chip is commonly coupled to the controller through an interrupt signal wire. The at least one memory chip generates at least one local interrupt signal and performs a logic operation on the at least one local interrupt signal to generate a common interrupt signal. The interrupt signal wire is configured to transmit the common interrupt signal to the controller.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Applicant: MACRONIX International Co., Ltd.Inventors: Jia-Xing Lin, Nai-Ping Kuo, Shih-Chou Juan, Chien-Hsin Liu, Shunli Cheng
-
Patent number: 11943525Abstract: An electronic camera assembly includes a camera chip cube bonded to camera bondpads of an interposer; at least one light-emitting diode (LED) bonded to LED bondpads of the interposer at the same height as the camera bondpads; and a housing extending from the interposer and LEDs to the height of the camera chip cube, with light guides extending from the LEDs through the housing to a top of the housing. In embodiments, the electronic camera assembly includes a cable coupled to the interposer. In typical embodiments the camera chip cube has footprint dimensions of less than three and a half millimeters square.Type: GrantFiled: February 17, 2022Date of Patent: March 26, 2024Assignee: OmniVision Technologies, Inc.Inventors: Teng-Sheng Chen, Wei-Ping Chen, Jau-Jan Deng, Wei-Feng Lin
-
Patent number: 11944016Abstract: A magnetoresistive random access memory, including a substrate, a conductive plug in the substrate, wherein the conductive plug has a notched portion on one side of the upper edge of the conductive plug, and a magnetic memory cell with a bottom electrode electrically connecting with the conductive plug, a magnetic tunnel junction on the bottom electrode and a top electrode on the magnetic tunnel junction, wherein the bottom surface of the magnetic memory cell and the top surface of the conductive plug completely align and overlap each other.Type: GrantFiled: March 11, 2022Date of Patent: March 26, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hung-Chan Lin, Yu-Ping Wang, Hung-Yueh Chen
-
Patent number: 11943875Abstract: A circuit board with anti-corrosion properties, a method for manufacturing the circuit board, and an electronic device are provided. The circuit board includes a circuit substrate, a first protective layer, and a second protective layer. The circuit substrate includes a base layer and an outer wiring layer formed on the base layer. The circuit substrate further defines a via hole connected to the outer wiring layer. The first protective layer is formed on the outer wiring layer and an inner sidewall of the via hole, and is made of a white oil. The second protective layer is formed on the first protective layer.Type: GrantFiled: May 10, 2022Date of Patent: March 26, 2024Assignee: CHAMP TECH OPTICAL (FOSHAN) CORPORATIONInventors: Li-Ping Wang, Yung-Ping Lin, Yong-Kang Zhang, Qiu-Ri Zhang, You-Zhi Lu
-
Patent number: 11942363Abstract: A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.Type: GrantFiled: August 9, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin
-
Publication number: 20240094559Abstract: A contact lens includes a central region, an annular region and a peripheral region. The central region includes a central point of the contact lens. The annular region symmetrically surrounds the central region. The peripheral region symmetrically surrounds the annular region. The peripheral region includes at least one color pattern portion. The annular region includes at least one power of critical point.Type: ApplicationFiled: November 27, 2023Publication date: March 21, 2024Inventors: En-Ping LIN, I-Wei LAI, Chun-Hung TENG
-
Publication number: 20240098932Abstract: A foldable electronic device, including a first body, a second body, an air valve movably disposed in the first body, at least one triggering member, and a hinge connecting the first body and the second body, is provided. The first body has multiple openings respectively located at two opposite surfaces. The triggering member is movably disposed in the first body and has a part exposed outside the first body. The air valve and the triggering member are mutually on moving paths of each other. The first body and the second body are rotated to be folded or unfolded relative to each other by the hinge. A part of the triggering member is suitable for bearing a force such that the triggering member drives the air valve, so that the air valve opens or closes the openings.Type: ApplicationFiled: July 19, 2023Publication date: March 21, 2024Applicant: Acer IncorporatedInventors: Hui-Ping Sun, Jui-Yi Yu, Chun-Hung Wen, Yen-Chou Chueh, Yu-Ming Lin, Chun-Hsien Chen
-
Publication number: 20240091766Abstract: Provided is a microfluidic device. The microfluidic device includes a first substrate and a second substrate disposed opposite to each other. A cavity is formed between the first substrate and the second substrate and configured to accommodate liquid. The first substrate includes multiple drive electrodes and multiple first electrodes, and the drive electrodes are disposed on a side of the first electrodes facing the second substrate. At least one of the drive electrodes includes at least one opening, and the at least one opening, along a direction perpendicular to a plane where the first substrate is located, penetrates the drive electrode where the at least one opening is located. An orthographic projection of at least one first electrode on the plane where the first substrate is located covers at least an orthographic projection of one opening on the plane where the first substrate is located.Type: ApplicationFiled: December 20, 2021Publication date: March 21, 2024Inventors: Kaidi ZHANG, Baiquan LIN, Kerui XI, Wei LI, Yunfei BAI, Ping SU
-
Publication number: 20240096705Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.Type: ApplicationFiled: November 30, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
-
Patent number: 11934549Abstract: One or more implementations of the present specification provide an invoice access method and apparatus based on a blockchain, and an electronic device. The method includes: generating first ciphertext data by encrypting plaintext data of the target invoice based on a first key corresponding to an invoice issuer; generating second ciphertext data by encrypting the plaintext data of the target invoice based on a second key corresponding to an invoice receiver; adding the first ciphertext data and an user identifier of the invoice issuer to the blockchain as related to one another; and adding the second ciphertext data and an user identifier of the invoice receiver to the blockchain as related to one another.Type: GrantFiled: August 31, 2021Date of Patent: March 19, 2024Assignee: Advance New Technologies Co., Ltd.Inventors: Hansong Xiao, Ping Zhang, Wenhu Kan, Qin Liu, Liangrong Lin, Fuxi Deng, Yixiang Zhang, Rui Chen, Jinming Duan
-
Patent number: 11936238Abstract: An uninterruptible power apparatus is coupled between a power grid and a load. The uninterruptible power apparatus includes a bypass path, a power conversion module, and a control module. The bypass path is coupled to the power grid through a grid terminal, and coupled to the load through a load terminal. The control module turns off a first thyristor and a second thyristor by injecting a second voltage into the load terminal during a forced commutation period. The control module calculates a magnetic flux offset amount based on an error amount between the second voltage and a voltage command, and provides a compensation command in response to the magnetic flux offset amount. The control module controls the DC/AC conversion circuit to provide a third voltage to the load terminal based on the compensation command and the voltage command.Type: GrantFiled: June 15, 2022Date of Patent: March 19, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Hsin-Chih Chen, Hung-Chieh Lin, Chao-Lung Kuo, Yi-Ping Hsieh, Chien-Shien Lee