Abstract: Disclosed are techniques for constructing a novel solder bump layout on substrates for bonding using flip-chip, wafer-level, or other similar techniques. In one embodiment, a method of manufacturing a semiconductor device provides for forming contact pads on a first substrate, and forming an isolation layer over the contact pads and the substrate. In addition the method includes forming openings in the isolation layer over the contact pads, and depositing metal in the openings and in electrical contact with the contact pads to form electrical contacts in the openings. Also in such embodiments, the method includes bonding exposed surfaces of the electrical contacts to corresponding bonding pads formed on an external surface of a second substrate. In these embodiments, the bonding is done such that the isolation layer is in contact with the external surface to provide electrical isolation between the first and second substrates and between the electrical contacts.

Abstract: An integrated circuit device with high Q MIM capacitor and its forming process are disclosed. The MIM capacitor dielectric layer is formed of a material which has relatively high dielectric constant and can be used as an anti-reflection coating (ARC). In the process of patterning MIM capacitor electrodes, the MIM capacitor dielectric layer can be directly used as an anti-reflection layer. Therefore, there is no need to form an anti-reflection layer on the metal layer, and the complexity and the cost of forming process can decrease.

Abstract: An integrated circuit device with high Q MIM capacitor and its forming process are disclosed. The MIM capacitor dielectric layer is formed of a material which has relatively high dielectric constant and can be used as an anti-reflection coating (ARC). In the process of patterning MIM capacitor electrodes, the MIM capacitor dielectric layer can be directly used as an anti-reflection layer. Therefore, there is no need to form an anti-reflection layer on the metal layer, and the complexity and the cost of forming process can decrease.

Abstract: The present invention provides a high-Q inductance device and a method for fabricating the same. The inductance device is formed on a semiconductor substrate and includes at least one spiral conducting line and a passivation layer formed above the spiral conducting line, the passivation layer including a spiral air gap formed within the space around the spiral conducting line. By means of the at least one spiral conducting line, the resistance of the inductance device can be decreased. Moreover, the parasitic capacitance can be decreased by means of the air gap with a low dielectric constant. Therefore, the Q value of the inductance device of the present invention can be effectively increased.

Abstract: An integrated circuit device with high Q MIM capacitor and its forming process are disclosed. The MIM capacitor dielectric layer is formed of a material which has relatively high dielectric constant and can be used as an anti-reflection coating (ARC). In the process of patterning MIM capacitor electrodes, the MIM capacitor dielectric layer can be directly used as an anti-reflection layer. Therefore, there is no need to form an anti-reflection layer on the metal layer, and the complexity and the cost of forming process can decrease.

Abstract: The present invention provides a method for fabricating a high-Q inductance device. First, a first dielectric layer is formed on a semiconductor substrate. A spiral conducting line is formed above the first dielectric layer. Then, a passivation layer is formed above the spiral conducting line and the first dielectric layer, such that a spiral air gap is formed in the passivation layer within the space around the spiral conducting line. Finally, the inductance device is immersed in an acid solution so as to increase the size of the spiral air gap. When an additional dielectric layer and spiral conducting line are formed between the first dielectric layer and the passivation layer, the air gap can be formed not only in the passivation layer, but also in the additional dielectric layer. Therefore, the inductance device of the present invention can have a plurality of air gaps that are formed in the passivation layer or formed in both of the passivation layer and the dielectric layers.

Abstract: A high inductance and high-Q inductor structure formed using multilevel interconnect technology with deep trench has the same current flow direction in each spiral coil pattern. The inductor uses reflection and rotation transformation to generate each spiral coil pattern and neighboring spiral coil pattern relatively rotates with respect to the lower spiral coil pattern. Each spiral coil connection follows the connection code of edge end to edge end and central end to central end through via plugs. Each spiral coil is connected in series and total inductance results from summation of each spiral coil pattern.

Abstract: The structure of a high-Q inductor applied in a monolithic circuit according to the invention comprises a plurality of spiral metal lines and a plurality of dielectric layers, each dielectric layer formed between two adjacent spiral metal lines. Furthermore, via plugs are formed in each dielectric layer to electrically connect two adjacent spiral metal lines. A spiral air trench is formed along the spacing of the spiral metal lines in the dielectric layers. Therefore, the 3D-structure of the inductor of the invention can greatly reduce the series resistance thereof without widening the spiral metal lines. In addition, the spiral air trench, filled with air which has a lower dielectric constant, can efficiently reduce the parasitic capacitance between the spacing of the spiral metal lines. As a result, the inductor of the invention has a higher quality factor at a proper RF operating frequency region.

Abstract: The present invention provides a method for fabricating a high-Q inductance device. First, a first dielectric layer is formed on a semiconductor substrate. A spiral conducting line is formed above the first dielectric layer. Then, a passivation layer is formed above the spiral conducting line and the first dielectric layer, such that a spiral air gap is formed in the passivation layer within the space around the spiral conducting line. Finally, the inductance device is immersed in an acid solution so as to increase the size of the spiral air gap. When an additional dielectric layer and spiral conducting line are formed between the first dielectric layer and the passivation layer, the air gap can be formed not only in the passivation layer, but also in the additional dielectric layer. Therefore, the inductance device of the present invention can have a plurality of air gaps that are formed in the passivation layer or formed in both of the passivation layer and the dielectric layers.

Abstract: The present invention provides a high-Q inductance device and a process for fabricating the same. The inductance device is formed on a semiconductor substrate and includes a first insulating layer, a second insulating layer, and a conducting coil. The first and second insulating layers are covered on different surfaces of the semiconductor substrate, respectively, and the second insulating layer has a lower dielectric constant than the first insulating layer. The conducting coil is formed on the second insulating layer. According to the present invention, the parasitic capacitance between the conducting coil and the substrate can be decreased by means of forming a conducting coil on an insulating layer having a low dielectric constant.

Abstract: The structure of high-Q inductor applied in a monolithic circuit according to the invention comprises a plurality of spiral metal lines and a plurality of dielectric layers, each dielectric layer formed between two adjacent spiral metal lines. Furthermore, via plugs are formed in each dielectric layer to electrically connect two adjacent spiral metal lines. A spiral air trench is formed along the spacing of the spiral metal lines in the dielectric layers. Therefore, 3D-structure of the inductor of the invention can greatly reduce the series resistance thereof without widening the spiral metal lines. In addition, the spiral air trench, filled with air which has a lower dielectric constant, can efficiently reduce the parasitic capacitance between the spacing of the spiral metal lines. As a result, the inductor of the invention has a higher quality factor at a proper RF operating frequency region.

Abstract: The structure of a high-Q inductor applied in a monolithic circuit according to the invention comprises a plurality of spiral metal lines and a plurality of dielectric layers, each dielectric layer formed between two adjacent spiral metal lines. Furthermore, via plugs are formed in each dielectric layer to electrically connect two adjacent spiral metal lines. A spiral air trench is formed along the spacing of the spiral metal lines in the dielectric layers. Therefore, the 3D-structure of the inductor of the invention can greatly reduce the series resistance thereof without widening the spiral metal lines. In addition, the spiral air trench, filled with air which has a lower dielectric constant, can efficiently reduce the parasitic capacitance between the spacing of the spiral metal lines. As a result, the inductor of the invention has a higher quality factor at a proper RF operating frequency region.

Abstract: A method for planarizing the surface of a semiconductor wafer is disclosed. It involves the steps of: (a) applying a coating solution containing a polymeric material on the dielectric film; (b) curing the polymeric material to cause the polymeric material to become hardened and form a polymeric layer; (c) subjecting the polymeric layer to a gas plasma treatment, so that at least a portion of the polymeric layer becomes a SiO2-like layer which can be polished by a conventional oxide-type CMP slurry; (d) depositing a PETEOS film on the SiO2-like layer; and (f) CMP polishing the PETEOS film and the SiO2-like laye using a conventional oxide-type CMP slurry. This method is particularly advantageous for fabricating semiconductor devices with relatively wide trenches wherein the polymer layer would warp into the bottom of the trench thus will not serve as an effective self-provided etch stop.

Abstract: A method for planarizing the surface of a semiconductor wafer is disclosed. It involves the steps of: (a) applying a coating solution containing a polymeric material on a semiconductor wafer having a non-planar surface; (b) curing the polymeric material to cause the polymeric material to become a hardened polymeric material; (c) subjecting the hardened polymeric material to a N.sub.2 O gas plasma treatment, so that an outer portion of the hardened polymeric material can be polished by a conventional CMP slurry which is typically intended for polishing silicon oxide; and (d) polishing the N.sub.2 O gas plasma treated polymeric material using a conventional CMP slurry. This method allows conventional CMP slurries to be used for the chemical-mechanical polishing of the chemically more inert polymeric material, thus eliminating stocking and potential compatibility problem. It also advantageously allows the unaffected portion of the polymeric material to serve as a self-provided etch stop.

Abstract: A three-dimension inductor structure formed in a conventional integrated circuit technology has a direction of magnetic field perpendicular to the normal direction of the substrate of an applied integrated circuit. Due to the direction of the magnetic field, the electromagnetic interference induced by the three-dimension inductor structure affects other components in the same integrated circuit slightly. The three-dimension inductor structure includes an N-turn coil. Each turn coil in the N-turn coil includes a first-level metal line, a second-level metal line and third-level metal line. The three levels of metal lines are separated from one another by isolating layers. Two nearby levels of metal lines are connected through via plugs in the isolating layers between them. The integral coil is accomplished by connecting the second-level metal line of the Nth turn coil to the third-level metal line of the (N+1)th turn coil.