Abstract: Embodiments described herein describe a power supply controller configured to control a power supply that provides power to an output load via a power supply transformer. The power supply controller includes a first terminal that provides supply voltage to the controller. The controller also includes a second terminal coupled to a switch external to the controller, the switch is part of a power converter controlled by the controller, wherein the second terminal is used for an initial power up of the power converter when the switch is turned on and used for a second functionality when the switch is turned off.

Abstract: An LED lamp comprises one or more LEDs, an inductive element coupled to an input voltage source and the one or more LEDs, and a switch coupled to the inductive element. A first current detector is coupled between the input voltage source and a ground node of the LED lamp, such that a current detected by the first current detector is proportional to a bulk voltage across the input voltage source. A second current detector is coupled between the inductive element and the ground node, such that current detected by the second current detector is proportional to a drain voltage across the switch. A switch controller controls the switch based on a feedback signal indicative of a voltage across the inductive element, which is generated based on a difference between the current detected by the second current detector and the current detected by the first current detector.

Abstract: An LED lamp comprises one or more LEDs, an inductive element coupled to an input voltage source and the one or more LEDs, and a switch coupled to the inductive element. A first current detector is coupled between the input voltage source and a ground node of the LED lamp, such that a current detected by the first current detector is proportional to a bulk voltage across the input voltage source. A second current detector is coupled between the inductive element and the ground node, such that current detected by the second current detector is proportional to a drain voltage across the switch. A switch controller controls the switch based on a feedback signal indicative of a voltage across the inductive element, which is generated based on a difference between the current detected by the second current detector and the current detected by the first current detector.

Abstract: Embodiments described herein describe a power supply controller configured to control a power supply that provides power to an output load via a power supply transformer. The power supply controller includes a first terminal that provides supply voltage to the controller. The controller also includes a second terminal coupled to a switch external to the controller, the switch is part of a power converter controlled by the controller, wherein the second terminal is used for an initial power up of the power converter when the switch is turned on and used for a second functionality when the switch is turned off.

Abstract: Methods are disclosed for performing analog to digital signal conversion in shorter time and/or with less power consumption. A predictive guess is supplied as a digital first signal. The digital first signal is converted (D/A) to a counterpart, analog guess signal. A comparison is made between the analog guess signal and a received, analog input sample signal. The result of the comparison is used to improve on the initially supplied guess in a next cycle. Fewer cycles and less power is consumed if the initial guess is within a certain range of the actual magnitude of the analog input sample signal.

Abstract: A voltage-to-current converter providing an output current with compensation for process-voltage-temperature (PVT) variations of a component in the voltage-to-current converter. The voltage-to-current converter includes a first voltage-to-current converter branch, a second voltage-to-current converter branch, and a compensation current path. The first voltage-to-current converter provides a first current to the output of the voltage-to-current converter based on a variable control voltage. The second voltage-to-current converter branch provides a second current based on a fixed voltage. The compensation current path provides a compensation current from the second voltage-to-current branch to the first voltage-to-current converter branch compensating variations in the first current caused by the PVT variations of the component in the first voltage-to-current converter branch.

Abstract: Methods and devices are disclosed for performing analog to digital signal conversion in shorter time and/or with less power consumption than that of a comparable analog to digital conversion that uses a conventional sequential approximation method based on a binary search. In one embodiment, a predictive guess is supplied as a digital first signal. The digital first signal is converted (D/A) to a counterpart, analog guess signal. A comparison is made between the analog guess signal and a received, analog input sample signal. The result of the comparison is used to improve on the initially supplied guess in a next cycle. Fewer cycles and less power is consumed if the initial guess is within a certain range of the actual magnitude of the analog input sample signal. In one embodiment, a digital modeler is used to model a process underlying the analog input sample signal and to thereby provide fairly good guesses.

Abstract: Methods and devices perform analog to digital signal conversion in shorter time and/or with less power consumption than that of a comparable analog to digital conversion that uses a conventional sequential approximation method based on a binary search. A predictive guess is supplied as a digital first signal. The digital first signal is converted (D/A) to a counterpart, analog guess signal. Fewer cycles and less power is consumed if the initial guess is within a certain range of the actual magnitude of the analog input sample signal. In one embodiment, a digital modeler is used to model a process underlying the analog input sample signal to thereby provide fairly good guesses.

Abstract: A low dropout (LDO) voltage regulator having more than one LDO modules, each LDO module having a frequency response adapted to a certain range of output frequency. The LDO voltage regulator can provide a gain over a broad range of operating frequency by combining output current from each LDO module and providing the combined current at an output of the LDO voltage regulator. The LDO voltage regulator further comprises a load monitor coupled to the LDO modules for disabling some of the LDO modules to reduce power consumption of the LDO voltage regulator.

Abstract: Methods and devices are disclosed for performing analog to digital signal conversion in shorter time and/or with less power consumption than that of a comparable analog to digital conversion that uses a conventional sequential approximation method based on a binary search. In one embodiment, a predictive guess is supplied as a digital first signal. The digital first signal is converted (D/A) to a counterpart, analog guess signal. A comparison is made between the analog guess signal and a received, analog input sample signal. The result of the comparison is used to improve on the initially supplied guess in a next cycle. Fewer cycles and less power is consumed if the initial guess is within a certain range of the actual magnitude of the analog input sample signal. In one embodiment, a digital modeler is used to model a process underlying the analog input sample signal and to thereby provide fairly good guesses.

Abstract: A flexible memory controller capable of performing any combination of read, write and deselect operations is described. The present invention can store two pending write or read operations and perform a third write or read operation. In a ZBT SRAM embodiment the memory controller has three address registers, two data registers, and two comparators. Addresses for pending memory access operations are shifted in the address registers so that memory access addresses can be stored without overwriting the memory addresses for the pending operations. Similarly, data is shifted in the data registers to ensure that data remains available for pending memory access operations. The specific register operations are controlled by a thirteen state state machine. The thirteen states and the relationships between the states are defined to enable the memory controller to perform any combination of read, write and deselect operations without inserting idle cycles.