Abstract: An OTP memory cell includes an antifuse transistor, a first transistor and a second transistor. The antifuse transistor includes a first fin, a second fin, a first gate structure, a first drain/source contact layer and a second drain/source contact layer. A central region of the first fin and a central region of the second fin are covered by a first gate structure. The first drain/source contact layer is electrically connected with a first terminal of the first fin and a first terminal of the second fin. The second drain/source contact layer is electrically connected with a second terminal of the second fin but not electrically connected with a second terminal of the first fin. The first transistor is connected with the first drain/source contact layer. The second transistor is connected with the second drain/source contact layer.

Abstract: A one-time-programmable (OTP) memory device includes an active region and a gate electrode layer. The active region includes a channel region having a channel layer and source/drain regions disposed on opposite sides of the channel region in a Y-direction. The gate electrode layer extends in an X-direction and wraps around the channel layer. A first thickness of the gate electrode layer from a first edge of a first end of the gate electrode layer to the channel layer in the X-direction is equal to a second thickness of the gate electrode layer from a second edge of a second end of the gate electrode layer to the channel layer in the X-direction. After the first end is connected to a first voltage and the second end is connected to a second voltage different to the first voltage, the first thickness is different to the second thickness.

Abstract: An antifuse-type one time programming memory includes a first memory cell. The first memory cell includes an antifuse transistor. The antifuse transistor includes a first nanowire, a first gate structure, a first drain/source structure and a second drain/source structure. The first nanowire is surrounded by the first gate structure. The first gate structure includes a first spacer, a second spacer, a first gate dielectric layer and a first gate layer. The first drain/source structure is electrically contacted with the first terminal of the first nanowire. The second drain/source structure is electrically contacted with the second terminal of the first nanowire.

Abstract: A one-time-programmable (OTP) memory device includes a memory array including an N-type memory cell and a P-type memory cell. The N-type memory cell includes first channel layers and second channel layers. The P-type memory cell includes third channel layers and fourth channel layers. The N-type memory cell and the P-type memory cell further include a first word-line gate structure extending in the Y-direction and wrapping around the first channel layers and the third channel layers, and an anti-fuse gate structure extending in the Y-direction and wrapping around the second channel layers and the fourth channel layers. The OTP memory device further includes a wall structure extending in an X-direction and between the N-type memory cell and the P-type memory cell in the Y-direction. The first channel layers, the second channel layers, the third channel layers, and the fourth channel layers attach on the wall structure.

Abstract: An OTP memory using a PUF technology includes a first memory cell. The first memory cell includes an antifuse transistor, a first select transistor and a second select transistor. The antifuse transistor includes a first nanowire, a second nanowire, a first gate structure, a first drain/source structure and a second drain/source structure. The first portions of the first nanowire and the second nanowire are contacted with the isolation wall. The second portions of the first nanowire and the second nanowire are covered by the first gate structure. The first drain/source structure is electrically connected with the first terminals of the first nanowire and the second nanowire. The second drain/source structure is electrically connected with a second terminal of the second nanowire, but not electrically connected with a second terminal of the first nanowire.

Abstract: An antifuse-type one time programming memory includes a first memory cell. The first memory cell includes at least one antifuse transistor. The antifuse transistor is forksheet transistor. The antifuse transistor includes a first nanowire, a first gate structure, a first drain/source structure and a second drain/source structure. A first-portion surface of the first nanowire is contacted with the isolation wall. A second-portion surface of the first nanowire is contacted with the first gate structure. The first gate structure includes a first spacer, a second spacer, a first gate dielectric layer and a first gate layer. The first drain/source structure is electrically contacted with a first terminal of the first nanowire. The second drain/source structure is electrically contacted with a second terminal of the first nanowire.

Abstract: An OTP memory cell for a PUFF technology includes a first select transistor, a first antifuse transistor and a second antifuse transistor. A first drain/source terminal of the first select transistor is connected with a bit line. A gate terminal of the first select transistor is connected with a word line. A gate terminal of the first antifuse transistor is connected with a second drain/source terminal of the first select transistor. Two drain/source terminals of the first antifuse transistor are connected with a first antifuse control line. A gate terminal of the second antifuse transistor is connected with a second drain/source terminal of the first select transistor. Two drain/source terminals of the second antifuse transistor are connected with a second antifuse control line.

Abstract: An antifuse-type OTP memory cell at least includes a first nanowire, a second nanowire, a first gate structure, a first drain/source structure and a second drain/source structure. The first gate structure includes a first gate dielectric layer, a second gate dielectric layer and a first gate layer. The first nanowire is surrounded by the first gate dielectric layer. The second nanowire is surrounded by the second gate dielectric layer. The first gate dielectric layer and the second gate dielectric layer are surrounded by the first gate layer. The first drain/source structure is electrically contacted with a first terminal of the first nanowire and a first terminal of the second nanowire. The second drain/source structure is electrically contacted with a second terminal of the first nanowire. The second drain/source structure is not electrically contacted with a second terminal of the second nanowire.

Abstract: An OTP memory cell includes an antifuse transistor, a first transistor and a second transistor. The antifuse transistor includes a first fin, a second fin, a first gate structure, a first drain/source contact layer and a second drain/source contact layer. A central region of the first fin and a central region of the second fin are covered by a first gate structure. The first drain/source contact layer is electrically connected with a first terminal of the first fin and a first terminal of the second fin. The second drain/source contact layer is electrically connected with a second terminal of the second fin but not electrically connected with a second terminal of the first fin. The first transistor is connected with the first drain/source contact layer. The second transistor is connected with the second drain/source contact layer.

Abstract: An antifuse-type one time programming memory cell at least includes an antifuse transistor. The antifuse transistor includes a first nanowire, a first gate structure, a first drain/source structure and a second drain/source structure. The first nanowire is surrounded by the first gate structure. The first gate structure comprises a first spacer, a second spacer, a first gate dielectric layer and a first gate layer. The first drain/source structure is electrically contacted with a first terminal of the first nanowire. The second drain/source structure is electrically contacted with a second terminal of the first nanowire.

Abstract: An antifuse-type one time programming memory cell includes a select device, a following device and an antifuse transistor. A first terminal of the select device is connected with a bit line. A second terminal of the select device is connected with a first node. A select terminal of the select device is connected with a word line. A first terminal of the following device is connected with the first node. A second terminal of the following device is connected with a second node. A control terminal of the following device is connected with a following control line. A first drain/source terminal of the antifuse transistor is connected with the second node. A gate terminal of the antifuse transistor is connected with an antifuse control line. A second drain/source terminal of the antifuse transistor is in a floating state.

Abstract: An antifuse-type one time programming memory cell includes a select device, a following device and an antifuse transistor. A first terminal of the select device is connected with a bit line. A second terminal of the select device is connected with a first node. A select terminal of the select device is connected with a word line. A first terminal of the following device is connected with the first node. A second terminal of the following device is connected with a second node. A control terminal of the following device is connected with a following control line. A first drain/source terminal of the antifuse transistor is connected with the second node. A gate terminal of the antifuse transistor is connected with an antifuse control line. A second drain/source terminal of the antifuse transistor is in a floating state.

Abstract: An antifuse-type one time programming memory cell, comprising: a first select transistor, wherein a first drain/source terminal of the first select transistor is connected with a bit line, and a gate terminal of the first select transistor is connected with a word line; an antifuse transistor, wherein a first drain/source terminal of the antifuse transistor is connected with a second drain/source terminal of the first select transistor, and a gate terminal of the antifuse transistor is connected with an antifuse control line; and a second select transistor, wherein a first drain/source terminal of the second select transistor is connected with a second drain/source terminal of the antifuse transistor, a gate terminal of the second select transistor is connected with the word line, and a second drain/source terminal of the second select transistor is connected with the bit line.

Abstract: An antifuse-type one time programming memory cell has following structures. A first doped region, a second doped region, a third doped region and a fourth doped region are formed in a well region. A gate oxide layer covers a surface of the well region. A first gate is formed on the gate oxide layer and spanned over the first doped region and the second doped region. The first gate is connected with a word line. A second gate is formed on the gate oxide layer and spanned over the third doped region and the fourth doped region. The second gate is connected with the word line. A third gate is formed on the gate oxide layer and spanned over the second doped region and the third doped region. The third gate is connected with an antifuse control line.

Abstract: An antifuse-type one time programming memory cell has following structures. A first doped region, a second doped region, a third doped region and a fourth doped region are formed in a well region. A gate oxide layer covers a surface of the well region. A first gate is formed on the gate oxide layer and spanned over the first doped region and the second doped region. The first gate is connected with a word line. A second gate is formed on the gate oxide layer and spanned over the third doped region and the fourth doped region. The second gate is connected with the word line. A third gate is formed on the gate oxide layer and spanned over the second doped region and the third doped region. The third gate is connected with an antifuse control line.