Abstract: Methods and apparatus for programming a ferroelectric memory according to various desired and constraining characteristics, such as the retention of the data written to the memory, the endurance of the memory itself, both retention and endurance, power consumption, constraints on available voltage levels, etc. The characteristics of the signal used to write the data to memory (e.g., voltage, power, etc.) are selected to as to satisfy the various desired and constraining characteristics.

Abstract: Exemplary embodiments of the present disclosure are directed to a bootstrapping module and logic circuits utilizing the bootstrapping module to compensate for a weak high condition. The bootstrapping module can be implemented using transistors have a single channel type that is the same as the channel type of transistors utilized in the logic circuits such that a truly unipolar circuit can be realized while addressing the weak high problem of such unipolar circuits.

Abstract: Exemplary embodiments of the present disclosure are directed to circuitry for effective operation of Ferroelectric-gated FET (FeFET) memories. Exemplary embodiment of the present disclosure includes circuits and/or circuit blocks to facilitate memory refresh, error checking and correcting (ECC), reading and sensing memory cells, program and erase operations, and other control and periphery operations for FeFET memory cell arrays.

Abstract: An electro-optic element includes a first waveguide, which is a plasmonic waveguide, including a first core having a ferroelectric material and a cladding having a first cladding portion. The first cladding portion includes, at a first interface with the ferroelectric material, a first cladding material. The electro-optic element includes a first and a second electrode for producing an electric field in the ferroelectric material when a voltage is applied between the first and second electrodes, for modulating a real part of a refractive index of the ferroelectric material. The element includes, in addition, a crystalline substrate on which the ferroelectric material is epitaxially grown with zero or one or more intermediate layers present between the substrate and the ferroelectric material. The element may have a second waveguide, which is a photonic waveguide, including for enabling evanescent coupling between the first and second waveguides.

Abstract: A cosmetic composition for whitening skin and a preparation method thereof The composition comprises the following components: pearl powder, pearl extract, glycyrrhiza glabra aqueous solution, hydrolyzed conchiolin protein and pea extract. The contents of the pearl powder and the pearl extract are not both zero, and the glycyrrhiza glabra aqueous solution contains 0.5 to 5.0% of the glycyrrhiza glabra extract.

Abstract: Exemplary embodiments of the present disclosure are directed to three-dimensional (3D) Ferroelectric-gated FET (FeFET) structures that can be used to implement circuitry include memory cells, memory arrays, and/or other logic-based circuitry. For example, in exemplary embodiments, 3D FeFET AND memory arrays with vertical and horizontal channel structures are provided.

Abstract: Methods and apparatus for programming a ferroelectric memory according to various desired and constraining characteristics, such as the retention of the data written to the memory, the endurance of the memory itself, both retention and endurance, power consumption, constraints on available voltage levels, etc. The characteristics of the signal used to write the data to memory (e.g., voltage, power, etc.) are selected to as to satisfy the various desired and constraining characteristics.

Abstract: Exemplary embodiments of the present disclosure are directed to circuitry for effective operation of Ferroelectric-gated FET (FeFET) memories. Exemplary embodiment of the present disclosure includes circuits and/or circuit blocks to facilitate memory refresh, error checking and correcting (ECC), reading and sensing memory cells, program and erase operations, and other control and periphery operations for FeFET memory cell arrays.

Abstract: Exemplary embodiments of the present disclosure are directed to a bootstrapping module and logic circuits utilizing the bootstrapping module to compensate for a weak high condition. The bootstrapping module can be implemented using transistors have a single channel type that is the same as the channel type of transistors utilized in the logic circuits such that a truly unipolar circuit can be realized while addressing the weak high problem of such unipolar circuits.

Abstract: Exemplary embodiments of the present disclosure are directed to three-dimensional (3D) Ferroelectric-gated FET (FeFET) structures that can be used to implement circuitry include memory cells, memory arrays, and/or other logic-based circuitry. For example, in exemplary embodiments, 3D FeFET AND memory arrays with vertical and horizontal channel structures are provided.

Abstract: The present invention discloses a method of forming a polygon-sectional rodlike ingot having an orientation marker or rounded corners, a rodlike ingot and a sheet substrate so formed. The method comprises: selecting one of sides of the polygon-sectional rodlike ingot that is parallel to an axial direction thereof as a first feature of a surface orientation marker; forming a minisize notch, which is parallel to an edge, in the one of sides selected as the first feature in the axial direction of the rodlike ingot, as a second feature of the orientation marker; and processing the rodlike ingot to form rounded corners. The sheet substrate is obtained by cutting the rodlike ingot.

Abstract: A metallic seal design that reduces manufacturing costs by minimizing production steps and also lowers the sealing force by incorporating a thin-wall, high height/width ratio annular column. The seal has two horizontal ribs which constrain the thin-wall column from unstable buckling to thereby reduce or eliminate the tendency of the sealing dams to become inclined to sealing flange surfaces.

Abstract: A metallic seal design that reduces manufacturing costs by minimizing production steps and also lowers the sealing force by incorporating a thin-wall, high height/width ratio annular column. The seal has two horizontal ribs which constrain the thin-wall column from unstable buckling to thereby reduce or eliminate the tendency of the sealing dams to become inclined to sealing flange surfaces.

Abstract: An electronic device is connected to an Inter-Integrated Circuit (I2C) expander using an I2C controller of the electronic device. The I2C expander is connected to the servers. Each of the servers corresponds to an identification number. Method of controlling baseboard management controller (BMC) of servers using the electronic device includes receiving identification numbers and determining an operation mode corresponding to each of the identification numbers. According to the identification numbers, each of the identification numbers corresponding to a determined server, servers are determined. The electronic device is controlled to connect to the determined servers. A restart server group comprising one or more determined servers whose operation modes are to restart BMC is determined. A restart signal is transmitted to the restart server group. A BMC of each of the one or more determined servers in the restart server group are controlled to restart according to the restart signal.

Abstract: Improvements in Complementary Metal Oxide Semiconductor (CMOS) devices; in particular, field effect transistors (FETs) and devices using said transistors which are able to take advantage of the higher carrier mobility of electrons compared to holes by replacing the conventional p-channel transistor with an n-channel transistor having a double gate (or vice versa): Such a. Unipolar CMOS (U-CMOS) transistor can be realized by adapting the source and/or the drain such that when the body region undergoes inversion at a first surface current, is able to flow between the drain and the source and when the body region undergoes inversion at a second surface current is not able to flow between the drain and the source. Various logic gates may be constructed using U-CMOS transistors.

Abstract: In a method for testing an aperture of the image capturing device, a brightness value range of images is divided into a plurality of range intervals, and one of the range intervals is determined for testing the aperture. A brightness value of a current image captured by the image capturing device is calculated. A diameter of the aperture is controlled to increase or decrease to change the brightness value of the current image to be within the determined range interval, if the brightness value is not within the determined range interval. After the brightness of the current is changed to be within the determined range interval, if the brightness value of the current image has been changed during a predetermined time period, it is determined that the aperture does not work normally.

Abstract: A health booth includes a telescopic and pivotal board including two telescopic units having one ends pivotably attached to a board; a seat assembly including two parallel columns mounted on the other side wall, a horizontal bar slidably put on the columns, a telescopic support post mounted between the horizontal bar and a bottom, and a collapsible seat secured to the horizontal bar, and a pivot assembly including a channel mounted onto one side wall, two torsion springs in the channel, two outer cylindrical members each together with one inner cylindrical member to dispose the other ends of the telescopic units therein, and two groups of a plurality of fasteners wherein each group of the fasteners are driven through the outer cylindrical member into the inner cylindrical member to fasten the other ends of the telescopic units.

Abstract: A health booth includes a telescopic and pivotal board including two telescopic units having one ends pivotably attached to a board; a seat assembly including two parallel columns mounted on the other side wall, a horizontal bar slidably put on the columns, a telescopic support post mounted between the horizontal bar and a bottom, and a collapsible seat secured to the horizontal bar, and a pivot assembly including a channel mounted onto one side wall, two torsion springs in the channel, two outer cylindrical members each together with one inner cylindrical member to dispose the other ends of the telescopic units therein, and two groups of a plurality of fasteners wherein each group of the fasteners are driven through the outer cylindrical member into the inner cylindrical member to fasten the other ends of the telescopic units.

Abstract: Improvements in Complementary Metal Oxide Semiconductor (CMOS) devices; in particular, field effect transistors (FETs) and devices using said transistors which are able to take advantage of the higher carrier mobility of electrons compared to holes by replacing the conventional p-channel transistor with an n-channel transistor having a double gate (or vice versa): Such a Unipolar CMOS (U-CMOS) transistor can be realised by adapting the source and/or the drain such that when the body region undergoes inversion at a first surface current, is able to flow between the drain and the source and when the body region undergoes inversion at a second surface current is not able to flow between the drain and the source. Various logic gates may be constructed using U-CMOS transistors.

Abstract: The invention of a method and an apparatus for reception of long transmission range Bluetooth signals impaired by multipath are disclosed. The new reception method and apparatus proposed allows to increase the transmission range for data transmission in Bluetooth. The invention proposes the use of a new FDE adapted to SC transmission without a GI or CP. The proposed FDE very successfully mitigates ISI while being very implementation-friendly.