Abstract: Methods, devices, systems, and techniques for dissecting a semiconductor wafer into multiple semiconductor devices are provided. In one aspect, the semiconductor device includes a circuit layer and a substrate. The semiconductor device includes four side surfaces and one or more notches extending into a portion of at least one of the four side surfaces, where a side wall of the one or more notches includes microcracks extend into the circuit layer, and where a remaining portion of the at least one of the four side surfaces is substantially flat and is intersected by the at least one of the one or more notches along the first direction; a portion of one or more of the four side surfaces is substantially flat and extending from a first surface to a second surface of the semiconductor device that are opposite to each other along the first direction.

Abstract: Implementations provide package structures, apparatuses, and methods for preparing the same. In an implementation, a package structure comprises: a mounting substrate; a first die disposed above the mounting substrate, the first die comprising a first main surface, a second main surface opposite to the first main surface, and an active device formed adjacent to the first main surface; and a second die interposed between the first die and the mounting substrate, wherein the first main surface of the first die faces towards the second die.

Abstract: Examples of the present disclosure provide a semiconductor structure and a fabrication method thereof and a semiconductor device, and relates to the field of semiconductor technology. The semiconductor structure includes a interposer layer and a bonding block that are stacked together. The bonding block includes a connection portion and a plurality of stacks, and the connection portion connects any two adjacent stacks. Any one of the stacks is bonded with the interposer layer. In the examples, the connection portion connects any two adjacent stacks, such that the plurality of stacks in the bonding block can be jointly bonded with the interposer layer, and there is no need to bond the plurality of stacks with the interposer layer separately, thereby improving production efficiency and unit per hour of the semiconductor structure and also improving convenience of bonding between the stacks and interposer layer, which facilitates miniaturization of the stacks.

Abstract: According to one aspect of the present disclosure, semiconductor device is provided. The semiconductor device may include a plurality of cutting lanes. The plurality of cutting lanes may include at least one first cutting lane. The plurality of cutting lanes may include a plurality of second cutting lanes disposed in parallel with the first cutting lane. The plurality of cutting lanes may include a third cutting lane disposed intersecting the first cutting lane and the second cutting lanes. The semiconductor device may include a plurality of dies defined by the intersection of the plurality of cutting lanes. The semiconductor device may include a die test structure only located in the first cutting lane. Any one of the at least one first cutting lane may be disposed adjacent to at least one of the plurality of second cutting lanes.

Abstract: Implementations of chip packaging structures, semiconductor structures and fabricating methods thereof are disclosed. A chip packaging structure comprises a substrate comprising: a signal transmitting wiring structure embedded in the substrate, and a thermal transmitting wiring structure embedded in the substrate. The chip packaging structure further comprises a first chip on the substrate and electrically connected with the signal transmitting wiring structure. The chip packaging structure further comprises at least one thermal conductive structure on the substrate, in thermal contact with the thermal transmitting wiring structure, and laterally surrounding the first chip.

Abstract: Examples of the present disclosure provide a wafer dicing device and a method of wafer dicing, the wafer dicing device including: a bearing platform, a first dicing sub device and a second dicing sub device, wherein the bearing platform is configured to bear the wafer to be diced, the first dicing sub device is configured to dice the wafer to be diced from a first side, and the second dicing sub device is configured to dice the wafer to be diced from a second side, the first side and the second side being opposite sides of the bearing platform in a first direction, the first direction being a direction of the thickness of the bearing platform.

Abstract: The present application discloses a semiconductor device and a fabrication method thereof, and a memory and a memory system. At least one cleavage plane guide structure extending along a second direction is disposed in a first cutting region adjacent to a first device region in a first direction in the semiconductor device, the second direction intersects the first direction, and the cleavage plane guide structure includes a first portion and a second portion that extend along the second direction, and the second portion has higher cleavage plane passability than the first portion. As such, a chip can cleave according to a preset direction and portion when stealth dicing is performed on the chip.

Abstract: The present disclosure provides a semiconductor device, a fabricating method thereof, a memory device and a memory system. The disclosed semiconductor device comprises a first device, a dicing street adjoining the first device laterally, a metal structure located in the dicing street, and a stealth cleavage lane extending in the dicing street.