Abstract: A method for controlling lattice defects at a junction is described, which is used in accompany with an ion implantation step for forming a junction in a substrate and a subsequent annealing step. In the method, an extra implantation step is performed to increase the stress in the substrate apart from the junction, such that enhanced recrystallization is induced in the annealing step to lower the stress at the junction. The extra implantation step can be performed before or after the ion implantation step for forming the junction. A method for forming LDD or S/D regions of a CMOS device is also described, wherein at least one extra implantation step as mentioned above is performed before, between or after the ion implantation steps for forming the LDD or S/D regions of NMOS and PMOS transistors.

Abstract: A method for forming a uniform doped region in a substrate having a non-uniform material layer thereon is provided. The non-uniform material layer is removed form the substrate. Thereafter, a treatment process is performed to form an offset material layer on a predetermined doped region of the substrate. Next, an ion implantation process is performed to form the uniform doped region in the predetermined doped region below the offset material layer.

Abstract: A method for fabricating a semiconductor device is provided. The method comprises: providing a substrate; forming a gate structure on the substrate, the gate structure including a gate dielectric layer on the substrate and a gate conductive layer on the gate dielectric layer; forming an oxide layer conformally covering the substrate and the gate structure; forming a dielectric layer covering the oxide layer; removing a portion of the dielectric layer to form a spacer on a sidewall of the gate structure, the oxide layer between the spacer and the gate structure as an oxide spacer; performing an oxygen plasma treatment process to form an silicon oxide layer in the substrate below the oxide layer, the silicon oxide layer and the oxide layer being an offset oxide layer; and forming a source/drain region in the substrate at two sides of the gate structure.

Abstract: A method for fabricating a semiconductor device is provided. The method comprises: providing a substrate; forming a gate structure on the substrate, the gate structure including a gate dielectric layer on the substrate and a gate conductive layer on the gate dielectric layer; forming an oxide layer conformally covering the substrate and the gate structure; forming a dielectric layer covering the oxide layer; removing a portion of the dielectric layer to form a spacer on a sidewall of the gate structure, the oxide layer between the spacer and the gate structure as an oxide spacer; performing an oxygen plasma treatment process to form an silicon oxide layer in the substrate below the oxide layer, the silicon oxide layer and the oxide layer being an offset oxide layer; and forming a source/drain region in the substrate at two sides of the gate structure.

Abstract: A method for controlling lattice defects at a junction is described, which is used in accompany with an ion implantation step for forming a junction in a substrate and a subsequent annealing step. In the method, an extra implantation step is performed to increase the stress in the substrate apart from the junction, such that enhanced recrystallization is induced in the annealing step to lower the stress at the junction. The extra implantation step can be performed before or after the ion implantation step for forming the junction. A method for forming LDD or S/D regions of a CMOS device is also described, wherein at least one extra implantation step as mentioned above is performed before, between or after the ion implantation steps for forming the LDD or S/D regions of NMOS and PMOS transistors.

Abstract: A method for fabricating a semiconductor device is provided. The method comprises: providing a substrate; forming a gate structure on the substrate, the gate structure including a gate dielectric layer on the substrate and a gate conductive layer on the gate dielectric layer; forming an oxide layer conformally covering the substrate and the gate structure; forming a dielectric layer covering the oxide layer; removing a portion of the dielectric layer to form a spacer on a sidewall of the gate structure, the oxide layer between the spacer and the gate structure as an oxide spacer; performing an oxygen plasma treatment process to form an silicon oxide layer in the substrate below the oxide layer, the silicon oxide layer and the oxide layer being an offset oxide layer; and forming a source/drain region in the substrate at two sides of the gate structure.

Abstract: A method for fabricating a semiconductor device is provided. The method comprises: providing a substrate; forming a gate structure on the substrate, the gate structure including a gate dielectric layer on the substrate and a gate conductive layer on the gate dielectric layer; forming an oxide layer conformally covering the substrate and the gate structure; forming a dielectric layer covering the oxide layer; removing a portion of the dielectric layer to form a spacer on a sidewall of the gate structure, the oxide layer between the spacer and the gate structure as an oxide spacer; performing an oxygen plasma treatment process to form an silicon oxide layer in the substrate below the oxide layer, the silicon oxide layer and the oxide layer being an offset oxide layer; and forming a source/drain region in the substrate at two sides of the gate structure.