Abstract: A gate driver and associated method for a double gate liquid crystal display (LCD) is disclosed. A gate driving signal generating circuit, such as coupled shift registers, generates the gate driving signals in response to horizontal synchronization signal. In one embodiment, a phase control circuit, such as logic AND gates, is coupled to receive the outputs of the shift registers for determining phase relationship between the outputs of the shift registers and the horizontal synchronization signal.

Abstract: A source driver for driving a display panel includes a sample/hold circuit, a first low voltage amplifier, a second low voltage amplifier, a first multiplexer, a high voltage amplifier, a second multiplexer, and a third multiplexer. The sample/hold circuit outputs a first sampled-held voltage and a second sampled-held voltage. The first and second low voltage amplifiers receives the first and second sampled-held voltages, respectively, and generates a first and second low pixel voltage, respectively. The first multiplexer outputs one of the first and second low pixel voltages according to a polarity signal. The high voltage amplifier ,generates a high pixel voltage. The second and third multiplexers output one of the first low pixel voltage and the high pixel voltage and one of the second low pixel voltage and the high pixel voltage, respectively, to a data line according to the polarity signal.

Abstract: A pixel circuit has a light emitting diode, a first driving transistor, a second driving transistor, a capacitor, and a switch unit. When a scan signal is asserted, the switch unit couples sources/drains of the second driving transistor respectively to a first and a second source/drain of the first driving transistor, and couples a gate and second source/drain of the first driving transistor together. When the scan signal is de-asserted, the switch unit decouples one of the sources/drains of the second driving transistor from the first/second source/drain of the first driving transistor, and decouples the gate from the second source/drain of the first driving transistor.

Abstract: A pixel circuit has a light emitting diode, a first driving transistor, a second driving transistor, a capacitor, and a switch unit. When a scan signal is asserted, the switch unit couples sources/drains of the second driving transistor respectively to a first and a second source/drain of the first driving transistor, and couples a gate and second source/drain of the first driving transistor together. When the scan signal is de-asserted, the switch unit decouples one of the sources/drains of the second driving transistor from the first/second source/drain of the first driving transistor, and decouples the gate from the second source/drain of the first driving transistor.

Abstract: A LCD driving circuit is provided herein. The LCD driving circuit includes a data processor for processing a plurality of data signals to generate a plurality of processed data signals to respectively drive a line of subpixels arranged on a LCD panel, a driving control module having a data sequence unit for receiving and arranging the processed data signal, and a switching control unit to generate a control signal and a plurality of driving signals corresponding with the control signal to drive a plurality of transistors, a source line driving circuit having a plurality of latching units to respectively store the processed data signal. Moreover, a driving method for LCD is also disclosed herein.

Abstract: A gate driver and associated method for a double gate liquid crystal display (LCD) is disclosed. A gate driving signal generating circuit, such as coupled shift registers, generates the gate driving signals in response to horizontal synchronization signal. In one embodiment, a phase control circuit, such as logic AND gates, is coupled to receive the outputs of the shift registers for determining phase relationship between the outputs of the shift registers and the horizontal synchronization signal.

Abstract: A liquid crystal display panel. The liquid crystal display panel comprises a first display matrix, a second display matrix, a first gate electrode group, a second gate electrode group and a data electrodes group. The first display matrix comprises first display cells arranged in N rows and M columns; the second display matrix comprises second display cells arranged in N rows and M columns. The first gate electrode group comprises first gate electrodes respectively coupled to the first display matrix and the second gate electrode group comprises second gate electrodes respectively coupled to the second display matrix. The data electrodes group comprises data electrodes respectively coupled to the first display matrix and the second display matrix, wherein an m-th data electrode is coupled to an m-th column of the first display cells and an m-th column of the second display cells.

Abstract: By adding multiplexing units to selectively transmit signals associated with a functional circuitry of an IC die to test pads, a probe card with less pin counts than the pad number of the IC die can be utilized for testing the functional circuitry. Therefore, the pad number/pad pitch of the IC die is not limited by the pitch of the conventional probe card. A high pin count IC die design is thereby available.

Abstract: A pixel circuit has a light emitting diode, a first driving transistor, a second driving transistor, a capacitor, and a switch unit. When a scan signal is asserted, the switch unit couples sources/drains of the second driving transistor respectively to a first and a second source/drain of the first driving transistor, and couples a gate and second source/drain of the first driving transistor together. When the scan signal is de-asserted, the switch unit decouples one of the sources/drains of the second driving transistor from the first/second source/drain of the first driving transistor, and decouples the gate from the second source/drain of the first driving transistor.

Abstract: A digital-to-analog converter and method for transforming a digital value into an analog signal are disclosed. The digital-to-analog converter has a voltage generator, a voltage selector, a multiplexer and a switch array. The voltage generator provides a first and second group of voltages. The voltage selector selectively outputs the first or second group of voltages according to a polarity signal. The multiplexer selectively outputs the digital value or a complementary value of the digital value according to the polarity signal. The switch array outputs one of the voltages received from the voltage selector according to the value output from the multiplexer.