Abstract: The coverification system includes a reconfigurable computing system (hereinafter “RCC computing system”) and a reconfigurable computing hardware array (hereinafter “RCC hardware array”). In some embodiments, the target system and the external I/O devices are not necessary since they can be modeled in software. In other embodiments, the target system and the external I/O devices are actually coupled to the coverification system to obtain speed and use actual data, rather than simulated test bench data. The RCC computing system contains a CPU and memory for processing data for modeling the entire user design in software. The RCC computing system also contains clock logic (for clock edge detection and software clock generation), test bench processes for testing the user design, and device models for any I/O device that the user decides to model in software instead of using an actual physical I/O device.

Abstract: The disclosed devices are several forms of a timing insensitive glitch-free (TIGF) logic device. The TIGF logic device can take the form of any latch or edge-triggered flip-flop. In one embodiment, a trigger signal is provided to update the TIGF logic device. The trigger signal is provided during a short trigger period that occurs at adjacent times from the evaluation period. In latch form, the TIGF latch includes a flip-flop that holds the current state of the TIGF latch until a trigger signal is received. A multiplexer is also provided to receive the new input value and the old stored value. The enable signal functions as the selector signal for the multiplexer. Because the trigger signal controls the updating of the TIGF latch, the data at D input to the TIGF latch and the control data at the enable input can arrive in any order without suffering from hold time violations.

Abstract: The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present.

Abstract: The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present.

Abstract: The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present.

Abstract: A method of simulating a system on a computer. The method comprises the following steps. First, analyze a hardware design language specification of the system to identify a set of processes. The hardware design language specification includes a register transfer level definition of a part of the system. Identify a set of triggered processes from the set of processes. Identify a set of triggers for the set of triggered processes, where a first trigger of the set of triggers is for causing a state change in a simulation of the system. Determine an evaluation order of the set of processes using the set of triggers. Simulate the system using the evaluation order.

Abstract: A method of preparing a specification of a system for simulation on a computer system. The specification includes a hardware design language specification of the system. Analyze the specification to identify a set of processes, where each process includes a plurality of statements. Determine an evaluation order of the set of processes. Generate a combined process including a portion of the plurality of statements. The portion of the plurality of statements are included in the combined process so as to be evaluated according to the evaluation order.