Abstract: The present invention discloses a real-time rate-control method for a video encoder chip, wherein a BU-based RC algorithm is realized in a pipeline architecture, and wherein the RC algorithm is divided into an UpdateQP part arranged before the IME stage and an UpdateModel part arranged behind the entropy stage. When a currently processed frame contains a plurality of macro blocks, the bits used by several leading macro blocks and the remaining bits are predicted. Only the average value of the MADs of the preceding frame is stored in the memory. Thereby, memory consumption is greatly reduced, and quantization parameters are obtained to predict the bit number required by the next frame. The present invention further defines a region of interest and automatically regulates the bit distribution ratio thereof to enhance the sharpness thereof.