Patents by Inventor Ping-Wang Chiang

Ping-Wang Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4576900
    Abstract: A process for forming on a substructure a plural layer, conductor interconnect pattern consisting of a plurality of successively formed, substantially planar, composite layers of insulating material and conductive material with said insulating material on each layer defining a pattern of regions filled with conductive material to serve as part of a vertical and horizontal interconnect system. The process includes the following steps for forming each composite layer:(a) forming a pattern of regions of conductive material on the substructure;(b) forming over the pattern of conductive regions a layer of insulating material to a thickness substantially greater than the thickness of the conductive material and having a substantially planar top surface; and(c) removing top surface portions of the layer of insulating material down to the top surface of the regions of conductive material.
    Type: Grant
    Filed: September 11, 1984
    Date of Patent: March 18, 1986
    Assignee: Amdahl Corporation
    Inventor: Ping-Wang Chiang
  • Patent number: 4442188
    Abstract: A system for specifying critical dimensions, mask sequence levels, and mask revision levels on integrated circuit photomasks and chips involving use of a patterned array of geometric regions containing preselected indicia in each region corresponding to the mask sequence number for an associated photomask. The preselected indicia may be either a critical diemension pattern to integrate the mask sequence indicia with the critical dimension specification or a mask revision level code to integrate the mask sequence number with the revision level, or a combination of both a critical dimension pattern and a mask revision level code. In the latter case the mask revision level code is integrated with the critical dimension pattern to conserve space on the photomask and the IC chip.
    Type: Grant
    Filed: January 2, 1981
    Date of Patent: April 10, 1984
    Assignee: Amdahl Corporation
    Inventor: Ping-Wang Chiang
  • Patent number: 4395438
    Abstract: A process for forming a silicon nitride layer on a semiconductor wafer in a low pressure chemical vapor deposition process. The wafer is disposed in a closed reaction chamber evacuated to a low pressure and heated to an elevated temperature in the range of about 650 to 900 degrees Centigrade. The interior of the chamber is supplied with a gaseous mixture of ammonia and a silicon compound adapted to react together with the ammonia at the elevated temperature to deposit a layer of silicon nitride on the wafer. The ammonia and the selected silicon compound have a ratio of relative concentrations in the mixture which is preselected to be in the range of 4:1 and 20:1. The silicon compound may be silane, dichlorosilane, or tetrachlorosilane. Using dichlorosilane, the preferred ratio of relative concentrations of ammonia and dichlorosilane is in the range of about 6:1 to 8:1.
    Type: Grant
    Filed: December 6, 1982
    Date of Patent: July 26, 1983
    Assignee: Amdahl Corporation
    Inventor: Ping-Wang Chiang
  • Patent number: 4343877
    Abstract: System for design and production of integrated circuit photomasks and integrated circuit devices wherein the four adjacent corners of each circuit topography pattern on each photomask and each wafer chip area are set aside as designated information locations. One of the designated information locations containing a two-dimensional rectangular array of locations for use as a mask sequence array and a second of the designated information locations containing a two-dimensional rectangular array of locations for use as an alignment key pattern array. The third designated information location serves as a product identification area which may include a manufacturer name and a product identification code. The fourth designated information location is adapted to serve as a test device area and may also serve as a part identification area in semiconductor processes employing a two layer metal interconnect system.
    Type: Grant
    Filed: January 2, 1981
    Date of Patent: August 10, 1982
    Assignee: Amdahl Corporation
    Inventor: Ping-Wang Chiang
  • Patent number: 4343878
    Abstract: A system for providing photomask alignment keys in semiconductor integrated circuit processing involving selecting a common photomask subarea to be utilized as an alignment key pattern area on each photomask in the set with the alignment key pattern area having an array of sequential key locations. Each photomask after the first has a designated alignment key location which is either the same alignment key location as the immediately preceding photomask or the next alignment key location in the array. A mask key pattern is formed on the first photomask comprising aligning keys for all the associated higher numbered photomasks designed to be aligned to topography created by use of the first photomask in accordance with a mask alignment formula with each of the aligning keys being formed at key locations corresponding to the designated alignment key locations for the associated photomask.
    Type: Grant
    Filed: January 2, 1981
    Date of Patent: August 10, 1982
    Assignee: Amdahl Corporation
    Inventor: Ping-Wang Chiang