Abstract: A method includes bonding a first package and a second package over a package component, adhering a first Thermal Interface Material (TIM) and a second TIM over the first package and the second package, respectively, dispensing an adhesive feature on the package component, and placing a heat sink over and contacting the adhesive feature. The heat sink includes a portion over the first TIM and the second TIM. The adhesive feature is then cured.

Abstract: The present application disclosures a double production line and a rapid prefabrication process of a segmental beam. The double production line including two production machine and a track system provided on the construction ground; the production machine includes a fixed end mold, two side molds, a bottom mold trolley, a middle internal mold trolley and two side internal mold trolley; two side molds are positioned on two sides of the fixed end mold respectively, the fixed end mold and two side molds together define a pouring position with an end opening, two openings of the pouring position are arranged facing each other; the track system includes a transverse track and a longitudinal track communicated with each other, two pouring positions are both positioned in the extension path of the transverse track, and the longitudinal track is positioned between two pouring positions.

Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.

Abstract: A memory unit with time domain edge delay accumulation for computing-in-memory applications is controlled by a first word line and a second word line. The memory unit includes at least one memory cell, at least one edge-delay cell multiplexor and at least one edge-delay cell. The at least one edge-delay cell includes a weight reader and a driver. The weight reader is configured to receive a weight and a multi-bit analog input voltage and generate a multi-bit voltage according to the weight and the multi-bit analog input voltage. The driver is connected to the weight reader and configured to receive an edge-input signal. The driver is configured to generate an edge-output signal having a delay time according to the edge-input signal and the multi-bit voltage. The delay time of the edge-output signal is positively correlated with the multi-bit analog input voltage multiplied by the weight.

Abstract: A magnetic multi-pole propulsion array system is applied to at least one external cathode and includes a plurality of magnetic multi-pole thrusters connected adjacent to each other. Each magnetic multi-pole thruster includes a propellant provider, a discharge chamber, an anode and a plurality of magnetic components. The propellant provider outputs propellant. The discharge chamber is connected with the propellant provider to accommodate the propellant. The anode is disposed inside the discharge chamber to generate an electric field. The plurality of magnetic components is respectively disposed on several sides of the discharge chamber. One of the several sides of the discharge chamber of the magnetic multi-pole thruster is applied for one side of a discharge chamber of another magnetic multi-pole thruster.

Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.

Abstract: Provided are methods of producing an acellular organ. The method includes the steps of, subjecting an organ derived from an animal to a static supercritical fluid (SCF) treatment followed by a dynamic SCF treatment. Optionally, the method of the present disclosure further includes a hypertonic and a hypotonic treatments prior to the static SCF treatment, and/or a neutralizing treatment after the dynamic SCF treatment. Also disclosed herein are acellular organs produced by the present method.

Abstract: A stator of a brushless motor is disclosed which includes a stator core, an insulating frame arranged on the stator core, and a plurality of windings wound around the insulating frame. The stator core includes a ring-shaped yoke part and a pole part mounted to the radial inner side of the yoke part. The pole part includes a plurality of teeth spaced-apart from each other along the circumferential direction, and a ring-shaped portion arranged at and connected to the radial inner side of the teeth. The radial outer sides of the teeth abut against the radial inner side of the yoke part. The insulating frame is arranged on the pole part. A plurality of power terminals are fixed to one axial end of the insulating frame and respectively electrically connected to the windings.

Abstract: A memory device includes a substrate, a first transistor and a second transistor, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate and are electrically connected to each other, in which each of the first and second transistors includes first semiconductor layers and second semiconductor layers, a gate structure, and source/drain structures, in which the first semiconductor layers are in contact with the second semiconductor layers, and a width of the first semiconductor layers is narrower than a width of the second semiconductor layers. The first word line is electrically connected to the gate structure of the first transistor. The second word line is electrically connected to the gate structure of the second transistor. The bit line is electrically connected to a first one of the source/drain structures of the first transistor.

Abstract: The present invention relates to a judgment method for edge node computing result trustworthiness based on trust evaluation, and belongs to the technical field of data processing. By means of the present invention, a security mechanism for trustworthiness of a computing result output by an industrial edge node is guaranteed, the industrial edge node is prevented from outputting error data, and attacks of false data of malicious edge nodes are resisted, it is guaranteed that trustworthy computing results not be tampered are input in the industrial cloud, and a site device is made to receive correct computing results rather than malicious or meaningless messages, thereby improving efficiency and security of industrial production.

Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing the same. The semiconductor structure includes a sensing device, a solar cell, and an interconnecting structure. The solar cell is disposed above the sensing device and is electrically connected to the sensing device. The interconnecting structure is disposed between the sensing device and the solar cell and has a first surface facing the solar cell and a second surface facing the sensing devices. The interconnecting structure comprises a first energy storage component and a second energy storage component. The first energy storage component is disposed closer to the first surface of the interconnecting structure than the second energy storage component.

Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.

Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.

Abstract: A system and computer-implemented method are provided for manufacturing a semiconductor electronic device. An assembler receives a jig and a boat supporting a die. The assembler includes a separator that separates the jig into a first jig portion and a second jig portion and a loader that positions the boat between the first jig portion and the second jig portion. A robot receives an assembly prepared by the assembler and manipulates a locking system that fixes an alignment of the boat relative to the first jig portion and the second jig portion to form a locked assembly. A process chamber receives the locked assembly and subjects the locked assembly to a fabrication operation.

Abstract: A single smart health device able to monitor all physiological aspects of a human body includes a body fluid detection module, a temperature detection module, an electrocardiogram detection module, and a control module. The body fluid detection module tests and detects amounts of biological substances in body fluids. The temperature detection module detects a temperature of the human body. The electrocardiogram detection module detects a heart rate of the human body. The control module is electrically connected to the body fluid detection module, the temperature detection module, and the electrocardiogram detection module, and obtains the detected amounts of biological substances, the detected temperature, and the detected heart rate.

Abstract: A switch short-circuited diagnosis method includes steps of: determining an initial voltage interval of multiple voltage intervals according to voltage relationships between voltages of a first phase wire, a second phase wire, and a third phase wire; performing a switch short-circuited diagnosis of a first bidirectional switch module in the three consecutive voltage intervals from the initial voltage interval, and including steps of: turning on a first switch branch, a second switch branch, or a third switch branch of the first bidirectional switch module according to the voltage relationships between the voltages of the first, second and third phase wires, determining whether an overcurrent occurs to diagnose whether the first switch branch, the second switch branch, or the third switch branch of the first bidirectional switch module is in a short-circuited state, and performing the switch short-circuited diagnosis for the next voltage interval.

Abstract: The present disclosure provides a method and device for dynamic recognition of emotion based on facial muscle movement monitoring, including: obtaining muscle movement data on one side and continuous frame images on the other side; obtaining multiple emotional states related to emotions, associating each emotional state with its corresponding continuous frame images, associating each emotional state with the muscle movement data corresponding to the continuous frame images at the same location and at the same time, to form a training set, building an emotion recognition model; inputting the muscle movement data and continuous frame images obtained in real time into the emotion recognition model to obtain a corresponding emotional state. This method builds an emotion recognition model through muscle movement data and continuous frame image, and uses motion data to make up for the parts of small action images that cannot be collected, thereby obtaining accurate emotion detection results.

Abstract: A semiconductor device includes a first source/drain feature on a front side of a substrate. The device includes a first backside metal line under the first source/drain feature and extending lengthwise along a first direction. The device includes a first backside via disposed between the first source/drain feature and the first backside metal line. The first backside metal line is a first bit line of a first static random access memory (SRAM) cell and is connected to the first source/drain feature through the first backside via. The first backside metal line includes a first portion and a second portion each extending widthwise along a second direction perpendicular to the first direction, the first portion is wider than the second portion, and the first portion partially lands on the first backside via. The first and the second portions are substantially aligned on one side along the first direction.