Abstract: Semiconductor structures and methods for fabricating semiconductor structures are provided. A semiconductor structure includes a first fin extending in an X-direction and a second fin parallel to the first fin and distanced from the first fin in a Y-direction perpendicular to the X-direction. Each fin is formed with a first device area and a second device area aligned in the X-direction; an isolation region disposed between the fins; an isolation structure disposed between the device areas in each fin; and an isolation layer disposed under the fins. The isolation region contacts the isolation layer, the isolation structure contacts the isolation layer, and the isolation region contacts the isolation structure to isolate the first fin from the second fin and to isolate the first device area from the second device area in each fin.

Abstract: A method according to the present disclosure includes receiving a structure. The structure includes a substrate, a first fin-shaped structure, a second fin-shaped structure, and a third fin-shaped structure disposed over the substrate, and a first isolation feature between the first fin-shaped structure and the second fin-shaped structure and a second isolation feature between the second fin-shaped structure and the third fin-shaped structure. The method further includes depositing a first dielectric layer over the first isolation feature and the second isolation feature, depositing a second dielectric layer over the first dielectric layer and the first isolation feature, but not over the second isolation feature, performing a first selective etching process to the first dielectric layer and the second dielectric layer, and performing a second selective etching process to the first dielectric layer over the second isolation feature.

Abstract: One aspect of the present disclosure pertains to a device. The device includes a memory macro having a frontside and a backside along a vertical direction. The memory macro includes edge strap areas extending lengthwise along a first direction at edges of the memory macro, a memory cell area having a plurality of memory cells, where the memory cell area is disposed between the edge strap areas along a second direction perpendicular to the first direction, and a middle strap area extending lengthwise along the first direction and disposed between the edge strap areas along the second direction, where the middle strap area divides the memory cell area into two memory cell domains. The middle strap area includes a feedthrough circuit that routes a power signal line of one of the plurality of memory cells to the backside of the memory macro.

Abstract: A semiconductor structure according to the present disclosure includes a first memory cell that includes a first pull-down transistor and a first pull-up transistor sharing a first gate structure extending along a first direction, a second pull-down transistor and a second pull-up transistor sharing a second gate structure extending along the first direction, a first pass-gate transistor having a third gate structure spaced apart but aligned with the second gate structure along the first direction, and a second pass-gate transistor having a fourth gate structure spaced apart but aligned with the first gate structure along the first direction, a frontside interconnect structure disposed over the first memory device, a backside interconnect structure disposed below the first memory device. A source of the second pull-down transistor is electrically coupled to the backside interconnect structure by way of a first backside contact via.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a first active region in which first semiconductor layers and second semiconductor layers are alternatingly stacked over a first lower fin element. In a plan view, the active region includes a first portion and a second portion narrower than the first portion. The method also includes removing the first semiconductor layers of the first active region. The second semiconductor layers of the first portion of the first active region form first nanostructures, and the second semiconductor layers of the second portion of the first active region form second nanostructures. The method also includes forming a first gate stack to surround the first nanostructures, and forming a second gate stack to surround the second nanostructures.

Abstract: An electronic memory device includes a memory-cell circuit. The electronic memory device also includes a non-memory-cell circuit. The non-memory cell circuit includes an active region. The active region extends in a first direction in a top view. The active region includes a first segment and a second segment. The first segment has a first dimension measured in a second direction in the top view. The second segment has a second dimension measured in the second direction different from the first direction in the top view. The second dimension is different from the first dimension.

Abstract: A semiconductor structure according to the present disclosure includes a first memory array in a first cache and a second memory array in a second cache. The first memory array includes a plurality of first memory cells arranged in M1 rows and N1 columns. The second memory array includes a plurality of second memory cells arranged in M2 rows and N2 columns. The semiconductor structure also includes a first bit line coupled to a number of N1 first memory cells in one of the M1 rows, and a second bit line coupled to a number of N2 second memory cells in one of the M2 rows. N1 is smaller than N2, and a width of the first bit line is smaller than a width of the second bit line.

Abstract: Well pick-up (WPU) regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary semiconductor device includes a circuit region, a first WPU region, second WPU region, a first well of a first conductivity type, and a second well of a second conductivity type. The circuit region, the first WPU region, and the second WPU region are arranged along a first direction in sequence. The first well has a first portion disposed in the circuit region and a second portion disposed in the first WPU region. The second well has a first portion disposed in the circuit region, a second portion disposed in the first WPU region, and a third potion disposed in the second WPU region. Measured along the first direction a width of the first WPU region is less than a width of the second WPU region.

Abstract: Optical inspection equipment for checking multiple utensils made of plant fibers contains: a delivery device, at least one light source, and at least one shooting device. The delivery device includes a carrier on which at least one transparent zone is defined, the at least one shooting device includes a first shooting device, the at least one light source includes a first light source, such that the first light source illuminates a respective one utensil to be translucent and the first shooting device shoots an image of the respective one utensil via the transparent zone of the carrier. Alternatively, the first light source illuminates the respective one utensil to be translucent via the transparent zone of the carrier and the first shooting device shoots the image of the respective one utensil directly.

Abstract: A semiconductor device according to the present disclosure includes a memory array having a plurality of memory cells arranged in a row, and an interconnect structure disposed over the memory cells and having a bit line coupled to each of the memory cells arranged in the row. The bit line has a first segment coupled to a first portion of the memory cells and a second segment coupled to a second portion of the memory cells. The first segment has a first width and the second segment has a second width that is smaller than the first width.

Abstract: A semiconductor device includes a first fin-shaped structure and a second fin-shaped structure on a substrate, a bump between the first fin-shaped structure and the second fin-shaped structure, a first recess between the first fin-shaped structure and the bump, and a second recess between the second fin-shaped structure and the bump. Preferably, a top surface of the bump includes a curve concave upward, a width of the bump is greater than twice the width of the first fin-shaped structure, and a height of the bump is less than one fourth of the height of the first fin-shaped structure.

Abstract: Semiconductor structures and methods are provided. An exemplary semiconductor structure according to the present disclosure includes a two-port static random access memory (SRAM) cell having a write port portion and a read port portion electrically coupled to the write port portion. The read port portion includes a transistor having a gate structure. The semiconductor structure also includes a first plurality of metal lines comprising a write bit line and a complementary write bit line are positioned at a first interconnect layer disposed over the gate structure and a read word line positioned at a second interconnect layer and electrically coupled to the gate structure, the second interconnect layer is disposed under the gate structure.

Abstract: Semiconductor structures and methods are provided. An exemplary semiconductor structure according to the present disclosure includes a two-port static random access memory (SRAM) cell having a write port portion and a read port portion electrically coupled to the write port portion. The read port portion includes a transistor having a first source/drain feature and a second source/drain feature. The semiconductor structure also includes a first plurality of metal lines comprising a write bit line and a complementary write bit line, wherein the first plurality of metal lines are positioned at a first metal interconnect layer, wherein the first metal interconnect layer is disposed over the first source/drain feature. The semiconductor structure also includes a read bit line positioned at a second metal interconnect layer, where the second metal interconnect layer is disposed under the first source/drain feature.

Abstract: An integrated circuit includes a first SRAM cell and a second SRAM cell, each including a plurality of field-effect transistors (FETs), a front metal line over the FETs and a back metal line below the FETs, and a middle strap area disposed between the first SRAM cell and the second SRAM cell. The middle strap area includes a plurality of gate stacks extending lengthwise along a direction, a gate isolation structure extending through a gate stack of the plurality of gate stacks, a feedthrough via (FTV) embedded in the gate isolation structure, a first dielectric gate disposed between the conductive structure and the first SRAM cell, and a second dielectric gate disposed between the conductive structure and the second SRAM cell. The FTV electrically couples the front metal line and the back metal line.

Abstract: A static random-access memory (SRAM) structure and the manufacturing method thereof are disclosed. An exemplary SRAM structure includes a first source/drain (S/D) feature and a second S/D feature formed in an interlayer dielectric layer (ILD) of a bit cell region of the SRAM structure, a frontside via electrically connecting to the first S/D feature, and a first backside via electrically connecting to the second S/D feature. The first S/D feature and the second S/D feature are of a same type.

Abstract: An interactive system combines an automated voice mechanism with a visual feedback mechanism. A first terminal device and a telecommunications server mutually transmit messages through a public switched telephone network. The first terminal device can send an input message to the telecommunications server and receive a voice feedback message from the telecommunications server. The telecommunications server can generate a processing message based on the input message and transmit the processing message to an information management server which based on the processing message's content, through an internet sends a forward message to an information distribution server which based on the forward message's content, sends a control message to a second terminal device. The second terminal device transmits a request message to a picture content management server according to the forward message to obtain a picture feedback message returned by the picture content management server.

Abstract: A method includes providing a substrate having a first region and a second region, forming a fin protruding from the first region, where the fin includes a first SiGe layer and a stack alternating Si layers and second SiGe layers disposed over the first SiGe layer and the first SiGe layer has a first concentration of Ge and each of the second SiGe layers has a second concentration of Ge that is greater than the first concentration, recessing the fin to form an S/D recess, recessing the first SiGe layer and the second SiGe layers exposed in the S/D recess, where the second SiGe layers are recessed more than the first SiGe layer, forming an S/D feature in the S/D recess, removing the recessed first SiGe layer and the second SiGe layers to form openings, and forming a metal gate structure over the fin and in the openings.

Abstract: Semiconductor devices having improved source/drain features and methods for fabricating such are disclosed herein. An exemplary device includes a semiconductor layer stack disposed over a mesa structure of a substrate. The device further includes a metal gate disposed over the semiconductor layer stack and an inner spacer disposed on the mesa structure of the substrate. The device further includes a first epitaxial source/drain feature and a second epitaxial source/drain feature where the semiconductor layer stack is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. The device further includes a void disposed between the inner spacer and the first epitaxial source/drain feature.

Abstract: A semiconductor structure includes a first source/drain (S/D) epitaxial feature, a second S/D epitaxial feature adjacent to the first S/D epitaxial feature, an insulating structure between the first and the second S/D epitaxial features, and a shared S/D contact over top surfaces of the first and the second S/D epitaxial features. A center portion of the shared S/D contact is directly between a side surface of the first S/D epitaxial feature and a side surface of the second S/D epitaxial feature. The center portion is directly above the insulating structure. The semiconductor structure further includes a backside via penetrating through the insulating structure to directly land on a bottom surface of the center portion.

Abstract: The present disclosure provides embodiments of electronic fuse devices. An electronic fuse device according to the present disclosure includes a first bit cell comprising a first plurality of active regions extending along a first direction and a second bit cell comprising a second plurality of active regions extending along the first direction. Each of the first plurality of active regions is aligned with one of the second plurality of active regions along the first direction. The first bit cell and the second bit cell are spaced apart along the first direction by a space and the space is free of a well tap cell.