Abstract: An optical system applied to an optical biometer is disclosed. The optical system includes a light source, first and second switchable reflectors, and first and second fixed reflectors. The first switchable reflector is disposed corresponding to the light source. The second switchable reflector is disposed corresponding to an eye. In a first mode, the first and second switchable reflectors are switched to a first state, and the incident light emitted by the light source is reflected by the first fixed reflector along a first optical path and then emitted to a first position of the eye. In a second mode, the first and second switchable reflectors are switched to a second state, and the incident light is sequentially reflected by the first switchable reflector, the second fixed reflector and the second switchable reflector along a second optical path and then emitted to a second position of the eye.

Abstract: A memory cell includes first through fifth gate structures that each extend along a first lateral direction, a first active structure extending along a second lateral direction and overlaid by respective first portions of the first to fourth gate structures, a second active structure extending along the second lateral direction and overlaid by respective second portions of the first to fourth gate structures, and a third active structure extending along the second lateral direction and overlaid by respective third portions of the third and fifth gate structures. In some embodiments, the first and second gate structures are aligned with each other, with the fourth and fifth gate structures aligned with a first segment and a second segment of the third gate structure, respectively. In some embodiments, the second lateral direction perpendicular to the first lateral direction.

Abstract: Techniques are described for power savings in wireless communication. A wireless communication method includes receiving, by a communication device, an indication information; and receiving, by the communication device, a first signal in at least one resource based on the indication information.

Abstract: Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.

Abstract: A magnetic device structure is provided. In some embodiments, the structure includes one or more first transistors, a magnetic device disposed over the one or more first transistors, a plurality of magnetic columns surrounding sides of the one or more first transistors and the magnetic device, a first magnetic layer disposed over the magnetic device and in contact with the plurality of magnetic columns, and a second magnetic layer disposed below the one or more first transistors and in contact with the plurality of magnetic columns.

Abstract: An image sensor device may include a pixel sensor array and a black level correction (BLC) region. The BLC region may include a sensing region in a substrate and a light-blocking layer above the sensing region. An anti-reflection array may be formed in the light-blocking layer. The anti-reflection array includes holes, trenches, and/or other structural features such that the light-blocking layer includes two or more areas in which the top surface of the light-blocking layer is at different heights in the image sensor device. The different heights of the top surface of the light-blocking layer reduce the likelihood of light being reflected off of the light-blocking layer and toward the pixel sensor array. The anti-reflection array may reduce the likelihood of occurrence of flares or hot spots in images generated by the image sensor device, which may increase the image quality of the images generated by the image sensor device.

Abstract: Semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor, a second transistor, a third transistor, and a plurality of shallow trench isolations. The first transistor is disposed in a medium-voltage region and includes a first plane, a first gate dielectric layer, and a first gate electrode. The second transistor is disposed in a boundary region and includes a second plane, a second gate dielectric layer, and a second gate electrode. The third transistor is disposed in a lower-voltage region and includes a third plane, a third gate dielectric layer, and a third gate electrode. The shallow trench isolations are disposed in the substrate, wherein top surfaces of the shallow trench isolations in the medium-voltage region, the boundary region and the low-voltage region are coplanar with top surfaces of the first gate dielectric layer and the second gate dielectric layer.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

Abstract: An universal probe card and a testing method are disclosed. The universal probe card includes a plurality of probes. The probes are configured to contact and test a plurality of different patterns to be tested. Each of the plurality of different patterns to be tested includes a plurality of portions to be tested. A pitch between the plurality of probes is a greatest common factor of pitches between the plurality of portions to be tested in the plurality of different patterns to be tested.

Abstract: A manufacturing method of a package structure includes: coupling a device package to a package substrate, where the device package includes semiconductor dies encapsulated by an insulating encapsulation and electrically coupled to the package substrate; forming a first dielectric pattern on the device package opposite to the package substrate, where the first dielectric pattern includes openings corresponding to the semiconductor dies of the device package; forming a thermal conductive material on the semiconductor dies of the device package and in the openings of the first dielectric pattern; placing a heat dissipating component over the device package and the package substrate, the heat dissipating component being in contact with the first dielectric pattern and the thermal conductive material; and performing a thermal treatment process on the first dielectric pattern and the thermal conductive material to form a thermal interface material structure coupling the heat dissipating component to the device pack

Abstract: The present invention relates to the field of yeast fermentations. More particularly, the invention relates to mutant alleles useful to engineer industrially relevant traits in yeast.

Abstract: The disclosure provides an electronic apparatus and a manufacturing method thereof. The electronic apparatus includes a first insulating layer, a first metal layer, a second metal layer, a PN junction assembly, and a transistor circuit. The first insulating layer includes a first surface and a second surface opposite to the first surface. The first metal layer is formed above the second surface. The second metal layer is formed on the second surface. The PN junction assembly is disposed on the first surface and electrically connected with the first metal layer and the second metal layer. The PN junction assembly includes a variable capacitor. The transistor circuit is electrically connecting with the second metal layer.

Abstract: A semiconductor structure includes a memory cell, a logic cell, and a transition region between the memory cell and the logic cell. The memory cell includes a first active region and a plurality of first gate structures with a gate pitch. The logic cell includes a second active region and a plurality of second gate structures with the gate pitch. The transition region includes a first dielectric feature and a second dielectric feature. The first dielectric feature divides the first active region into a first segment partially in the transition region and a second segment fully in the transition region. The second dielectric feature divides the second active region into a third segment partially in the transition region and a fourth segment fully in the transition region.

Abstract: A memory cell includes first and second active regions extending lengthwise in a first direction, and first, second, third, and fourth gate structures arranged in order from first to fourth along the first direction. Each of the first, second, third, and fourth gate structures extends lengthwise in a second direction that is perpendicular to the first direction. The first, second, third, and fourth gate structures are configured to engage the first and second active regions in forming first, second, third, fourth, fifth, and sixth transistors of a write-port of the memory cell. The memory cell also includes a fifth gate structure configured to engage the second active region in forming a seventh transistor of a read-port of the memory cell.

Abstract: A semiconductor structure includes a memory cell, one or more logic cells configured to provide logic function to the memory cell, and an interconnect structure disposed over the memory cell and the one or more logic cells. The interconnect structure includes a bit line, a bit line bar, a first voltage line, and a second voltage line located in a same metal line layer of the interconnect structure. At least one of the bit line and the bit line bar extends from inside a boundary of the one or more logic cells and into a boundary of the memory cell. At least one of the first and second voltage lines extends from inside the boundary of the one or more logic cells and into the boundary of the memory cell.

Abstract: A memory cell includes a first active region providing a plurality of first nano-structures for a write-port pass-gate transistor, a second active region providing a plurality of second nano-structures for a write-port pull-up transistor, and a third active region providing a plurality of third nano-structures for a read-port pull-down transistor. The first active region has a first width, the second active region has a second width, and the third active region having a third width. The third width is larger than the first width, and the first width is larger than the second width.

Abstract: A memory cell includes a device layer including a plurality of transistors and an interconnect structure disposed over the device layer. Each of the transistors includes a gate structure extending lengthwise in a first direction. The interconnect structure includes a bottommost metal line layer electrically coupled to the transistors in the device layer. The bottommost metal line layer includes metal lines arranged in first, second, third, fourth, fifth, and sixth metal tracks in order from first to sixth along the first direction. A distance between any adjacent two of the first, second, third, fourth, fifth, and six metal tracks measured along the first direction is uniform. The first metal track includes a metal line electrically coupled to an electric ground of the memory cell. The sixth metal track includes a metal line electrically coupled to a power supply of the memory cell.

Abstract: A method of forming a semiconductor structure includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, forming cladding layers along sidewalls of the fin structure, forming a dummy gate stack over the cladding layers, and forming source/drain (S/D) features in the fin structure and adjacent to the dummy gate stack. The method further includes removing the dummy gate stack to form a gate trench adjacent to the S/D features, removing the cladding layers to form first openings along the sidewalls of the fin structure, where the first openings extend to below the stack, removing the first semiconductor layers to form second openings between the second semiconductor layers and adjacent to the first openings, and subsequently forming a metal gate stack in the gate trench, the first openings, and the second openings.

Abstract: The disclosure provides an electronic apparatus. The electronic apparatus includes an insulator, a driving unit, an electronic unit, and a circuit unit. The driving unit is overlapped with the insulator. The electronic unit is overlapped with the insulator. The circuit unit is electrically connected to the driving unit. The driving unit receives a signal from the circuit unit and drives the electronic unit.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first fin structure and a second fin structure over the substrate. A top surface of the first fin structure and a top surface of the second fin structure are at different height levels. The semiconductor device structure also includes a first semiconductor element on the first fin structure and a second semiconductor element on the second fin structure. The first semiconductor element is wider than the second semiconductor element, and the first semiconductor element is closer to the substrate than the second semiconductor element.