Patents by Inventor Ping-Wen Chen

Ping-Wen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11968817
    Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Lin Chen, Chao-Yuan Chang, Ping-Wei Wang, Fu-Kai Yang, Ting Fang, I-Wen Wu, Shih-Hao Lin
  • Patent number: 11810923
    Abstract: A pixel array substrate includes data lines, first gate lines, pixel structures, first common lines, and conductive line sets. The conductive line sets are arranged in a first direction. Each of the conductive line sets includes first conductive line groups and a second conductive line group sequentially arranged in the first direction. Each of the first conductive line groups includes second gate lines and a second common line. The second conductive line group includes first auxiliary lines and a second common line. An arrangement order of the second gate lines and the second common line of each of the first conductive line groups in the first direction are the same as an arrangement order of the first auxiliary lines and the second common line of the second conductive line group in the first direction, respectively.
    Type: Grant
    Filed: February 22, 2023
    Date of Patent: November 7, 2023
    Assignee: AUO Corporation
    Inventors: Ping-Wen Chen, Min-Tse Lee, Sheng-Yen Cheng, Yueh-Hung Chung, Yueh-Chi Wu, Shu-Wen Liao, Ti-Kuei Yu, Ya-Ling Hsu, Chen-Hsien Liao
  • Patent number: 11705462
    Abstract: An electronic device includes a substrate, multiple transversal signal lines, a first vertical signal line, a second vertical signal line, a shielding wire, and multiple pixel structures. The first vertical signal line is intersected with the transversal signal lines. The second vertical signal line is intersected with the transversal signal lines and connected to one of the transversal signal lines. An orthogonal projection of the shielding wire on the substrate is located between an orthogonal projection of the first vertical signal line and an orthogonal projection of the second vertical signal line on the substrate. One of the pixel structures is surrounded by a corresponding one of the transversal signal lines and the second vertical signal line and includes an active device. A gate and a source of the active device is electrically connected to the corresponding one transversal signal line and the first vertical signal line respectively.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: July 18, 2023
    Assignee: Au Optronics Corporation
    Inventors: Ya-Ling Hsu, Min-Tse Lee, Ti-Kuei Yu, Yueh-Chi Wu, Shu-Wen Liao, Hung-Chia Liao, Yueh-Hung Chung, Jia-Hong Wang, Ping-Wen Chen, Sheng-Yen Cheng, Chen-Hsien Liao
  • Publication number: 20230197736
    Abstract: A pixel array substrate includes data lines, first gate lines, pixel structures, first common lines, and conductive line sets. The conductive line sets are arranged in a first direction. Each of the conductive line sets includes first conductive line groups and a second conductive line group sequentially arranged in the first direction. Each of the first conductive line groups includes second gate lines and a second common line. The second conductive line group includes first auxiliary lines and a second common line. An arrangement order of the second gate lines and the second common line of each of the first conductive line groups in the first direction are the same as an arrangement order of the first auxiliary lines and the second common line of the second conductive line group in the first direction, respectively.
    Type: Application
    Filed: February 22, 2023
    Publication date: June 22, 2023
    Applicant: AUO Corporation
    Inventors: Ping-Wen Chen, Min-Tse Lee, Sheng-Yen Cheng, Yueh-Hung Chung, Yueh-Chi Wu, Shu-Wen Liao, Ti-Kuei Yu, Ya-Ling Hsu, Chen-Hsien Liao
  • Patent number: 11610920
    Abstract: A pixel array substrate includes data lines, first gate lines, pixel structures, first common lines, and conductive line sets. The conductive line sets are arranged in a first direction. Each of the conductive line sets includes first conductive line groups and a second conductive line group sequentially arranged in the first direction. Each of the first conductive line groups includes second gate lines and a second common line. The second conductive line group includes first auxiliary lines and a second common line. An arrangement order of the second gate lines and the second common line of each of the first conductive line groups in the first direction are the same as an arrangement order of the first auxiliary lines and the second common line of the second conductive line group in the first direction, respectively.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: March 21, 2023
    Assignee: Au Optronics Corporation
    Inventors: Ping-Wen Chen, Min-Tse Lee, Sheng-Yen Cheng, Yueh-Hung Chung, Yueh-Chi Wu, Shu-Wen Liao, Ti-Kuei Yu, Ya-Ling Hsu, Chen-Hsien Liao
  • Patent number: 11586085
    Abstract: A display apparatus including data lines, first gate lines, pixel structures, second gate lines, and first common lines is provided. The data lines are arranged in a first direction. The first gate lines are arranged in a second direction. The data lines and the second gate lines are arranged in the first direction, and the second gate lines are electrically connected to the first gate lines. The pixel structures are arranged in pixel columns which are arranged in the first direction. Each of the first common lines and the corresponding second gate line are configured between two adjacent pixel columns. The first common line and the corresponding second gate line are configured respectively on the opposite sides of the first gate line which is electrically connected to the corresponding second gate line. The first common line and the corresponding second gate line are structurally separated.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: February 21, 2023
    Assignee: Au Optronics Corporation
    Inventors: Sheng-Yen Cheng, Min-Tse Lee, Hung-Chia Liao, Jia-Hong Wang, Ping-Wen Chen, Yueh-Hung Chung, Ya-Ling Hsu, Chen-Hsien Liao
  • Patent number: 11520190
    Abstract: An electronic device including a substrate, transversal signal lines, a first vertical signal line, a second vertical signal line, and a first shielding vertical line is provided. The transversal signal lines, the first vertical signal line, the second vertical signal line, and the first shielding vertical line are disposed on the substrate. The first vertical signal line and the second vertical signal line are intersected with the transversal signal lines. The second vertical signal line is connected to one of the transversal signal lines. An orthogonal projection of the first shielding vertical line on the substrate is between an orthogonal projection of the first vertical signal line on the substrate and an orthogonal projection of the second vertical signal line on the substrate.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: December 6, 2022
    Assignee: Au Optronics Corporation
    Inventors: Yueh-Hung Chung, Min-Tse Lee, Sheng-Yen Cheng, Ping-Wen Chen, Jia-Hong Wang, Ti-Kuei Yu, Ya-Ling Hsu, Chen-Hsien Liao
  • Patent number: 11502114
    Abstract: A display panel including sub-pixels, first and second scan lines, first and second data lines, and first to fourth auxiliary lines is provided. The sub-pixels are arranged into first rows arranged in a first direction and second rows arranged in a second direction. Each third auxiliary line is electrically connected to a second auxiliary line and a first auxiliary line electrically connected to a first scan line. Each fourth auxiliary line is electrically connected to a second scan line and a first scan line. There are at least 2n second rows between each third auxiliary line and the first scan line electrically connected thereto, there are at least 2n+1 second rows between each third auxiliary line and the second scan line electrically connected thereto, and n is a positive integer.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: November 15, 2022
    Assignee: Au Optronics Corporation
    Inventors: Jia-Hong Wang, Min-Tse Lee, Sheng-Yen Cheng, Ping-Wen Chen, Hung-Chia Liao, Yueh-Hung Chung, Ya-Ling Hsu, Chen-Hsien Liao
  • Patent number: 11462148
    Abstract: A pixel array substrate includes a substrate, a plurality of data lines, a plurality of scan lines, a plurality of sub-pixels, and a first and a second auxiliary lines. The plurality of sub-pixels are arranged into first rows arranged in a first direction and second rows arranged in a second direction. The first auxiliary line and the plurality of scan lines belong to a first conductive layer. The second auxiliary line and the plurality of data lines belong to a second conductive layer. The first auxiliary line is located between two scan lines. A first end of the first auxiliary line is connected to one of the two scan lines. A second end of the first auxiliary line is separated from the other one of the two scan lines. The second auxiliary line is electrically connected to the first auxiliary line at the second end through a conductive via.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: October 4, 2022
    Assignee: AU Optronics Corporation
    Inventors: Min-Tse Lee, Sheng-Yen Cheng, Ping-Wen Chen, Yueh-Hung Chung, Ya-Ling Hsu, Chen-Hsien Liao
  • Patent number: 11362168
    Abstract: A display panel including sub pixels, a plurality of first and second scan lines, a plurality of first and second data lines, a plurality of first and second auxiliary lines and first conductive vias is provided. The sub pixels are arranged into first rows arranged in a first direction and second rows arranged in a second direction. The second rows are electrically connected to the first and second scan lines in alternation and are electrically connected to the first and second data lines in alternation. Each first auxiliary line includes a first portion electrically connected to a corresponding first scan line and a second portion spaced away from the first portion. The second auxiliary lines are respectively located between two adjacent first rows. Each second scan line is electrically connected to a corresponding first scan line through at least one second auxiliary line.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: June 14, 2022
    Assignee: Au Optronics Corporation
    Inventors: Jia-Hong Wang, Min-Tse Lee, Sheng-Yen Cheng, Yueh-Hung Chung, Han-Ming Chen, Ping-Wen Chen, Hung-Chia Liao, Ya-Ling Hsu, Chen-Hsien Liao
  • Publication number: 20220137466
    Abstract: An electronic device including a substrate, transversal signal lines, a first vertical signal line, a second vertical signal line, and a first shielding vertical line is provided. The transversal signal lines, the first vertical signal line, the second vertical signal line, and the first shielding vertical line are disposed on the substrate. The first vertical signal line and the second vertical signal line are intersected with the transversal signal lines. The second vertical signal line is connected to one of the transversal signal lines. An orthogonal projection of the first shielding vertical line on the substrate is between an orthogonal projection of the first vertical signal line on the substrate and an orthogonal projection of the second vertical signal line on the substrate.
    Type: Application
    Filed: January 13, 2022
    Publication date: May 5, 2022
    Applicant: Au Optronics Corporation
    Inventors: Yueh-Hung Chung, Min-Tse Lee, Sheng-Yen Cheng, Ping-Wen Chen, Jia-Hong Wang, Ti-Kuei Yu, Ya-Ling Hsu, Chen-Hsien Liao
  • Publication number: 20210175255
    Abstract: A pixel array substrate includes data lines, first gate lines, pixel structures, first common lines, and conductive line sets. The conductive line sets are arranged in a first direction. Each of the conductive line sets includes first conductive line groups and a second conductive line group sequentially arranged in the first direction. Each of the first conductive line groups includes second gate lines and a second common line. The second conductive line group includes first auxiliary lines and a second common line. An arrangement order of the second gate lines and the second common line of each of the first conductive line groups in the first direction are the same as an arrangement order of the first auxiliary lines and the second common line of the second conductive line group in the first direction, respectively.
    Type: Application
    Filed: September 11, 2020
    Publication date: June 10, 2021
    Applicant: Au Optronics Corporation
    Inventors: Ping-Wen Chen, Min-Tse Lee, Sheng-Yen Cheng, Yueh-Hung Chung, Yueh-Chi Wu, Shu-Wen Liao, Ti-Kuei Yu, Ya-Ling Hsu, Chen-Hsien Liao
  • Publication number: 20210056887
    Abstract: A pixel array substrate includes a substrate, a plurality of data lines, a plurality of scan lines, a plurality of sub-pixels, and a first and a second auxiliary lines. The plurality of sub-pixels are arranged into first rows arranged in a first direction and second rows arranged in a second direction. The first auxiliary line and the plurality of scan lines belong to a first conductive layer. The second auxiliary line and the plurality of data lines belong to a second conductive layer. The first auxiliary line is located between two scan lines. A first end of the first auxiliary line is connected to one of the two scan lines. A second end of the first auxiliary line is separated from the other one of the two scan lines. The second auxiliary line is electrically connected to the first auxiliary line at the second end through a conductive via.
    Type: Application
    Filed: August 4, 2020
    Publication date: February 25, 2021
    Applicant: Au Optronics Corporation
    Inventors: Min-Tse Lee, Sheng-Yen Cheng, Ping-Wen Chen, Yueh-Hung Chung, Ya-Ling Hsu, Chen-Hsien Liao
  • Publication number: 20210057508
    Abstract: A display panel including sub pixels, a plurality of first and second scan lines, a plurality of first and second data lines, a plurality of first and second auxiliary lines and first conductive vias is provided. The sub pixels are arranged into first rows arranged in a first direction and second rows arranged in a second direction. The second rows are electrically connected to the first and second scan lines in alternation and are electrically connected to the first and second data lines in alternation. Each first auxiliary line includes a first portion electrically connected to a corresponding first scan line and a second portion spaced away from the first portion. The second auxiliary lines are respectively located between two adjacent first rows. Each second scan line is electrically connected to a corresponding first scan line through at least one second auxiliary line.
    Type: Application
    Filed: August 17, 2020
    Publication date: February 25, 2021
    Applicant: Au Optronics Corporation
    Inventors: Jia-Hong Wang, Min-Tse Lee, Sheng-Yen Cheng, Yueh-Hung Chung, Han-Ming Chen, Ping-Wen Chen, Hung-Chia Liao, Ya-Ling Hsu, Chen-Hsien Liao
  • Publication number: 20210057452
    Abstract: An electronic device includes a substrate, multiple transversal signal lines, a first vertical signal line, a second vertical signal line, a shielding wire, and multiple pixel structures. The first vertical signal line is intersected with the transversal signal lines. The second vertical signal line is intersected with the transversal signal lines and connected to one of the transversal signal lines. An orthogonal projection of the shielding wire on the substrate is located between an orthogonal projection of the first vertical signal line and an orthogonal projection of the second vertical signal line on the substrate. One of the pixel structures is surrounded by a corresponding one of the transversal signal lines and the second vertical signal line and includes an active device. A gate and a source of the active device is electrically connected to the corresponding one transversal signal line and the first vertical signal line respectively.
    Type: Application
    Filed: August 17, 2020
    Publication date: February 25, 2021
    Applicant: Au Optronics Corporation
    Inventors: Ya-Ling Hsu, Min-Tse Lee, Ti-Kuei Yu, Yueh-Chi Wu, Shu-Wen Liao, Hung-Chia Liao, Yueh-Hung Chung, Jia-Hong Wang, Ping-Wen Chen, Sheng-Yen Cheng, Chen-Hsien Liao
  • Publication number: 20210057449
    Abstract: A display panel including sub-pixels, first and second scan lines, first and second data lines, and first to fourth auxiliary lines is provided. The sub-pixels are arranged into first rows arranged in a first direction and second rows arranged in a second direction. Each third auxiliary line is electrically connected to a second auxiliary line and a first auxiliary line electrically connected to a first scan line. Each fourth auxiliary line is electrically connected to a second scan line and a first scan line. There are at least 2n second rows between each third auxiliary line and the first scan line electrically connected thereto, there are at least 2n+1 second rows between each third auxiliary line and the second scan line electrically connected thereto, and n is a positive integer.
    Type: Application
    Filed: June 19, 2020
    Publication date: February 25, 2021
    Applicant: Au Optronics Corporation
    Inventors: Jia-Hong Wang, Min-Tse Lee, Sheng-Yen Cheng, Ping-Wen Chen, Hung-Chia Liao, Yueh-Hung Chung, Ya-Ling Hsu, Chen-Hsien Liao
  • Publication number: 20210055611
    Abstract: An electronic device including a substrate, transversal signal lines, a first vertical signal line, a second vertical signal line, and a first shielding vertical line is provided. The transversal signal lines, the first vertical signal line, the second vertical signal line, and the first shielding vertical line are disposed on the substrate. The first vertical signal line and the second vertical signal line are intersected with the transversal signal lines. The second vertical signal line is connected to one of the transversal signal lines. An orthogonal projection of the first shielding vertical line on the substrate is between an orthogonal projection of the first vertical signal line on the substrate and an orthogonal projection of the second vertical signal line on the substrate.
    Type: Application
    Filed: August 14, 2020
    Publication date: February 25, 2021
    Applicant: Au Optronics Corporation
    Inventors: Yueh-Hung Chung, Min-Tse Lee, Sheng-Yen Cheng, Ping-Wen Chen, Jia-Hong Wang, Ti-Kuei Yu, Ya-Ling Hsu, Chen-Hsien Liao
  • Publication number: 20210055615
    Abstract: A display apparatus including data lines, first gate lines, pixel structures, second gate lines, and first common lines is provided. The data lines are arranged in a first direction. The first gate lines are arranged in a second direction. The data lines and the second gate lines are arranged in the first direction, and the second gate lines are electrically connected to the first gate lines. The pixel structures are arranged in pixel columns which are arranged in the first direction. Each of the first common lines and the corresponding second gate line are configured between two adjacent pixel columns. The first common line and the corresponding second gate line are configured respectively on the opposite sides of the first gate line which is electrically connected to the corresponding second gate line. The first common line and the corresponding second gate line are structurally separated.
    Type: Application
    Filed: July 27, 2020
    Publication date: February 25, 2021
    Applicant: Au Optronics Corporation
    Inventors: Sheng-Yen Cheng, Min-Tse Lee, Hung-Chia Liao, Jia-Hong Wang, Ping-Wen Chen, Yueh-Hung Chung, Ya-Ling Hsu, Chen-Hsien Liao
  • Patent number: 8917362
    Abstract: A touch-sensitive display device has an active display area and a non-active area and includes a touch-sensitive unit, a display unit and a liquid optical adhesive. The touch-sensitive unit has a touch-sensitive region substantially overlapping the active display area, and the display unit is disposed on one side of the touch-sensitive unit. The liquid optical adhesive is disposed between the touch-sensitive unit and the display unit to combine the touch-sensitive unit with the display unit, and an outer edge of the liquid optical adhesive is located in the non-active area of the touch-sensitive display device.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: December 23, 2014
    Assignee: Wintek Corporation
    Inventors: Wen-Chun Wang, Ming-Sin Jian, San-Shien Wu, Ming-Chuan Lin, Chiu Wen Lo, Wen-Hung Wang, Shyh-Jeng Chen, Ping-Wen Chen
  • Publication number: 20110304572
    Abstract: A touch-sensitive display device has an active display area and a non-active area and includes a touch-sensitive unit, a display unit and a liquid optical adhesive. The touch-sensitive unit has a touch-sensitive region substantially overlapping the active display area, and the display unit is disposed on one side of the touch-sensitive unit. The liquid optical adhesive is disposed between the touch-sensitive unit and the display unit to combine the touch-sensitive unit with the display unit, and an outer edge of the liquid optical adhesive is located in the non-active area of the touch-sensitive display device.
    Type: Application
    Filed: June 10, 2011
    Publication date: December 15, 2011
    Inventors: Wen-Chun WANG, Ming-Sin Jian, San-Shien Wu, Ming-Chuan Lin, Chiu Wen Lo, Wen-Hung Wang, Shyh-Jeng Chen, Ping-Wen Chen