Abstract: The present invention discloses a piping design for a high density plasma process chamber, wherein an extra pipe is added to between a process chamber and a mass flow controller, and the extra pipe together with a pump is used to drain out the gas, which cannot be monitored by the mass flow controller and survives in a gas injection pipe, lest the remaining gas pollute the deposited film or react with the process gas to induce an explosion in the succeeding deposition process.

Abstract: A method for fabricating a flash memory is described. A stacked gate structure and a source/drain are formed on a substrate. An inter-layer dielectrics and a plurality of inter-metal dielectric layers are then formed over the substrate, wherein at least one layer among the inter-layer dielectrics and the inter-metal dielectric layers has a silicon carbide layer formed thereon. The silicon carbide layer is formed to protect the memory device from an UV irradiation, so as to prevent data errors occurring in the memory device.

Abstract: The present invention provides a method for forming a flash memory cell and comprises following steps. First, a substrate is provided. Then, a gate dielectric layer, a first polysilicon layer and a hard mask layer are sequentially formed on the substrate. Next, a portion of the hard mask layer, the polysilicon layer, and the gate dielectric layer are removed to form a plurality of holes to expose the substrate. Following, a dielectric layer is formed in those holes by a HDPCVD process. Last, the hard mask layer on the first polysilicon layer is removed by the HDPCVD process. Further, a second polysilicon layer could be conformally formed on the first polysilicon layer and the isolation dielectric.

Abstract: A method for fabricating a flash memory is described. A stacked gate structure and a source/drain are formed on a substrate. An inter-layer dielectrics and a plurality of inter-metal dielectric layers are then formed over the substrate, wherein at least one layer among the inter-layer dielectrics and the inter-metal dielectric layers has a silicon carbide layer formed thereon. The silicon carbide layer is formed to protect the memory device from an UV irradiation, so as to prevent data errors occurring in the memory device.

Abstract: A method of forming a shallow trench isolation structure. A pad oxide layer and a mask layer are sequentially formed over a substrate. A portion of the pad oxide layer, mask layer and substrate are removed to form a trench in the substrate. A first stage high-density plasma chemical vapor deposition having a high etching/deposition ratio is conducted to form a layer of insulation material over the substrate. A second stage high-density plasma chemical vapor deposition having a lower etching/deposition rate is conducted to form a second layer of insulation material over the substrate and completely fills the trench. Insulating material outside the trench region is removed. Finally, the mask layer and the pad oxide layer are sequentially removed to form a complete STI structure.

Abstract: A stacked mask layer, comprising a pad oxide layer and a stop layer, is formed with at least one opening on a substrate to expose portions of a surface of the substrate. Thereafter, a dry etching process is performed to etch the surface of the substrate through the opening to form a shallow trench. By performing a chemical vapor deposition (CVD) process, a CVD liner layer is formed on both the surface of the stacked mask layer and the surface of the shallow trench. The CVD liner layer is oxidized to form an oxidized liner layer, and a dielectric layer is formed on the oxidized liner layer to fill the shallow trench. By performing a planarization process, both portions of the dielectric layer and the oxidized liner layer atop the stop layer are removed to expose the stop layer. The stop layer is finally removed.

Abstract: A method of forming a shallow trench isolation structure. A pad oxide layer and a mask layer are sequentially formed over a substrate. A portion of the pad oxide layer, mask layer and substrate are removed to form a trench in the substrate. A first stage high-density plasma chemical vapor deposition having a high etching/deposition ratio is conducted to form a layer of insulation material over the substrate. A second stage high-density plasma chemical vapor deposition having a lower etching/deposition rate is conducted to form a second layer of insulation material over the substrate and completely fills the trench. Insulating material outside the trench region is removed. Finally, the mask layer and the pad oxide layer are sequentially removed to form a complete STI structure.

Abstract: The present invention provides a method for forming a flash memory cell and comprises following steps. First, a substrate is provided. Then, a gate dielectric layer, a first polysilicon layer and a hard mask layer are sequentially formed on the substrate. Next, a portion of the hard mask layer, the polysilicon layer, and the gate dielectric layer are removed to form a plurality of holes to expose the substrate. Following, a dielectric layer is formed in those holes by a HDPCVD process. Last, the hard mask layer on the first polysilicon layer is removed by the HDPCVD process. Further, a second polysilicon layer could be conformally formed on the first polysilicon layer and the isolation dielectric.

Abstract: The present invention provides a method for forming a flash memory cell and comprises following steps. First, a substrate is provided. Then, a first polysilicon layer and a nitride layer are sequentially formed on the substrate. Next, a portion of the nitride layer and the polysilicon layer are removed to form a plurality of holes to expose the substrate. Following, an isolation dielectric is formed in those holes, wherein the isolation dielectric is gibbous in a sidewall of those holes and higher than the first polysilicon layer. Then, the nitride layer on the first polysilicon layer is removed. Last, a second polysilicon layer is conformally formed on the first polysilicon layer and the isolation dielectric.

Abstract: A method of forming memory cell having buried diffusion oxide is disclosed. The method comprises the steps of providing a substrate having a tunnel oxide layer and a first conductive layer thereon, forming trenches into said tunnel oxide layer and said first conductive layer to expose said substrate, filling said trenches with a dielectric material to a predetermined thickness, removing a portion of said first conductive layer to form a surface lower than said predetermined thickness; and forming a second conductive layer over said dielectric material and said first conductive layer.

Abstract: A method for manufacturing dielectric layers between metal parts by forming fluorine silicate glass by high density plasma deposition using radio frequency power of low bias voltage. The method includes filling in a gap with fluorine silicate glass by high density plasma deposition with slower rate of deposition and radio frequency power of high bias voltage, and then using fluorine silicate glass deposited with fast rate of deposition and radio frequency power of no or low bias voltage as a sacrificial layer, and being made plane by a chemical-mechanic polishing CMP.

Abstract: The present invention provides an infrared spectroscopic method of removing a first layer from a semiconductor wafer without overpolishing the underlying second layer. The first layer and the second layer of the semiconductor wafer is subjected to infrared (IR) spectroscopy and an absorbance curve is produced, whereby each layer absorbs IR light at different wavenumbers to produce different absorbance peaks. Once the CMP process is performed, a change in the IR absorptivity and thus the absorbance peak of each layer is detected. The endpoint of the CMP process is determined at a point when significant change in the IR absorptivity of the first layer is no longer detected and change in the IR absorptivity of the second layer occurs.