Patents by Inventor Ping Yin

Ping Yin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11973005
    Abstract: A method includes bonding a first package and a second package over a package component, adhering a first Thermal Interface Material (TIM) and a second TIM over the first package and the second package, respectively, dispensing an adhesive feature on the package component, and placing a heat sink over and contacting the adhesive feature. The heat sink includes a portion over the first TIM and the second TIM. The adhesive feature is then cured.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hsun Wang, Ping-Yin Hsieh, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
  • Publication number: 20240135675
    Abstract: Detecting fine-grained similarity in image includes determining a core area of a search image by generating an image salient map from a plurality of layers of the search image and determining a connected area based on the image salient map. Feature descriptors are generated from the core area of the search image. A plurality of capsule vectors are generated from different ones of a plurality of keypoints of the feature descriptors. Capsule vectors of the search image are compared with capsule vectors of each image of the dataset to generate a top-K matrix. Similarity scores for the top-K matrix are calculated. One or more image of the dataset having fine-grained similarity with the search image are selected based a bundled similarity score for each image of the dataset. The bundled similarity score is a summation of the similarity scores of the image.
    Type: Application
    Filed: October 23, 2022
    Publication date: April 25, 2024
    Inventors: Fei Wang, Xue Ping Liu, Dan Zhang, Yun Jing Zhao, Kun Yan Yin, Zhi Xing Peng, Jian Long Sun
  • Publication number: 20240126000
    Abstract: The technology of this application relates to a frontlight module and a display apparatus. The frontlight module is disposed on a side of a display panel. The frontlight module includes a light source, a light guide plate, and light guide dots. The light guide plate includes a first surface and a second surface that are disposed opposite to each other. The display panel is disposed facing the second surface. The light source is disposed on a side surface of the light guide plate. A plurality of light guide dots are disposed on the first surface or the second surface of the light guide plate. Each light guide dot has a light guide surface disposed at an angle with respect to a surface of the light guide plate. Light is fully reflected and/or refracted on the light guide surfaces to propagate to the display panel.
    Type: Application
    Filed: December 15, 2023
    Publication date: April 18, 2024
    Inventors: Jifeng Tan, Feng Liao, Qiang Wang, Xiaoshan Chen, Han Yin, Liang Yuan, Ping Pan
  • Publication number: 20240119563
    Abstract: One or more systems, devices, computer program products and/or computer-implemented methods of use provided herein relate to detecting a closed ring in a three-dimensional (3D) point cloud via cycle basis. A system can comprise a memory configured to store computer executable components; and a processor configured to execute the computer executable components stored in the memory, wherein the computer executable components can comprise a filtering component that can filter a first undirected graph of a three-dimensional (3D) point cloud, by eliminating one or more edges of the first undirected graph that are longer than an adaptive threshold, wherein filtering the first undirected graph can produce a second undirected graph; and a detection component that can detect a minimum cycle basis of the second undirected graph to determine a cycle path that can traverse an irregular annular shape that is represented by the 3D point cloud.
    Type: Application
    Filed: October 5, 2022
    Publication date: April 11, 2024
    Inventors: Xue Ping Liu, Fei Wang, Dan Zhang, Kun Yan Yin, Yun Jing Zhao, Jian Long Sun, Zhi Xing Peng
  • Publication number: 20240104830
    Abstract: A computer-implemented method, system and computer program product for improving accuracy of a vision model. Images of an object with a first set of perspectives are received from a dataset used to train the vision model. A three-dimensional model of the object is then generated using the images of the object from the dataset. Using the three-dimensional model of the object, images of the object with a second set of perspectives are obtained. For example, the second set of perspectives may include different perspectives than the perspectives of the object from the images contained in the dataset. The dataset used to train the vision model may then be augmented with such images of the object with a second set of perspectives. In this manner, the dataset used to train the vision model includes a greater number of perspectives of the object thereby improving the accuracy of the vision model.
    Type: Application
    Filed: September 24, 2022
    Publication date: March 28, 2024
    Inventors: Kun Yan Yin, Xue Ping Liu, Yun Jing Zhao, Fei Wang, Yu Tao Wu, Yue Liu
  • Patent number: 11932534
    Abstract: A microelectromechanical system (MEMS) structure and method of forming the MEMS device, including forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, where the first metallization structure includes a first sacrificial oxide layer and a first metal contact pad. A second metallization structure is formed over a MEMS wafer, where the second metallization structure includes a second sacrificial oxide layer and a second metal contact pad. The first metallization structure and second metallization structure are then bonded together. After the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer to form a MEMS element over the second sacrificial oxide layer. After the MEMS element is formed, removing the first sacrificial oxide layer and second sacrificial oxide layer to allow the MEMS element to move freely about an axis.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Hua Lin, Chang-Ming Wu, Chung-Yi Yu, Ping-Yin Liu, Jung-Huei Peng
  • Publication number: 20240087879
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 14, 2024
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 11919948
    Abstract: The invention provides isoform-selective anti-TGF? antibodies and methods of using the same. In particular, isoform-selective anti-TGF?2, anti-TGF?3, and anti-TGF?2/3 monoclonal antibodies are provided, e.g., for the treatment of fibrosis and other TGF?-related disorders.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: March 5, 2024
    Assignee: GENENTECH, INC.
    Inventors: Wei-Ching Liang, Joseph R. Arron, Daryle Depianto, Wendy Green Halpern, WeiYu Lin, Patrick J. Lupardus, Thirumalai Rajan Ramalingam, Dhaya Seshasayee, Tianhe Sun, Tulika Tyagi, Jia Wu, Yan Wu, Jian Ping Yin
  • Publication number: 20240071847
    Abstract: A semiconductor package including two different adhesives and a method of forming are provided. The semiconductor package may include a package component having a semiconductor die bonded to a substrate, a first adhesive over the substrate, a heat transfer layer on the package component, and a lid attached to the substrate by a second adhesive. The first adhesive may encircle the package component and the heat transfer layer. The lid may include a top portion on the heat transfer layer and the first adhesive, and a bottom portion attached to the substrate and encircling the first adhesive. A material of the second adhesive may be different from a material of the first adhesive.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Inventors: Yi-Huan Liao, Ping-Yin Hsieh, Chih-Hao Chen, Pu Wang, Li-Hui Cheng, Ying-Ching Shih
  • Patent number: 11894408
    Abstract: A device includes two BSI image sensor elements and a third element. The third element is bonded in between the two BSI image sensor elements using element level stacking methods. Each of the BSI image sensor elements includes a substrate and a metal stack disposed over a first side of the substrate. The substrate of the BSI image sensor element includes a photodiode region for accumulating an image charge in response to radiation incident upon a second side of the substrate. The third element also includes a substrate and a metal stack disposed over a first side of the substrate. The metal stacks of the two BSI image sensor elements and the third element are electrically coupled.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ping-Yin Liu, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen, Pin-Nan Tseng
  • Publication number: 20240038623
    Abstract: In an embodiment, a device includes a package component including an integrated circuit die and conductive connectors connected to the integrated circuit die, the conductive connectors disposed at a front-side of the package component. The device also includes a back-side metal layer on a back-side of the package component. The device also includes an indium thermal interface material on a back-side of the back-side metal layer. The device also includes a lid on a back-side of the indium thermal interface material. The device also includes a package substrate connected to the conductive connectors, the lid being adhered to the package substrate.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Inventors: Ping-Yin Hsieh, Chih-Hao Chen, Yi-Huan Liao, Pu Wang, Li-Hui Cheng
  • Publication number: 20240014100
    Abstract: A method includes bonding a first package and a second package over a package component, adhering a first Thermal Interface Material (TIM) and a second TIM over the first package and the second package, respectively, dispensing an adhesive feature on the package component, and placing a heat sink over and contacting the adhesive feature. The heat sink includes a portion over the first TIM and the second TIM. The adhesive feature is then cured.
    Type: Application
    Filed: August 7, 2023
    Publication date: January 11, 2024
    Inventors: Yu-Hsun Wang, Ping-Yin Hsieh, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 11854795
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 11854999
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes bonding structure arranged directly between a first substrate and a second substrate. The first substrate includes a first transparent material and a first alignment mark. The first alignment mark is arranged on an outer region of the first substrate and also includes the first transparent material. The first alignment mark is defined by surfaces of the first substrate that are arranged between an uppermost surface of the first substrate and a lowermost surface of the first substrate. The second substrate includes a second alignment mark on an outer region of the second substrate. The second alignment mark directly underlies the first alignment mark, and the bonding structure is arranged directly between the first alignment mark and the second alignment mark.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu
  • Publication number: 20230378017
    Abstract: An embodiment is a device including a package component including an integrated circuit die and conductive connectors connected to the integrated circuit die, the conductive connectors disposed at a first side of the package component. The device also includes a metal layer on a second side of the package component, the second side being opposite the first side. The device also includes a thermal interface material on the metal layer. The device also includes a lid on the thermal interface material. The device also includes a retaining structure on sidewalls of the package component and the thermal interface material. The device also includes a package substrate connected to the conductive connectors, the lid being adhered to the package substrate.
    Type: Application
    Filed: August 19, 2022
    Publication date: November 23, 2023
    Inventors: Ping-Yin Hsieh, Pu Wang, Li-Hui Cheng, Ying-Ching Shih, Hung-Yu Chen
  • Publication number: 20230378020
    Abstract: A method includes placing a package, which includes a first package component, a second package component, and an encapsulant encapsulating the first package component and the second package component therein. The method further includes attaching a first thermal interface material over the first package component, attaching a second thermal interface material different from the first thermal interface material over the second package component, and attaching a heat sink over both of the first thermal interface material and the second thermal interface material.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 23, 2023
    Inventors: Ping-Yin Hsieh, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
  • Publication number: 20230371354
    Abstract: The present disclosure relates to a processing tool that includes a first wafer-mounting frame and a second wafer-mounting frame. The first wafer-mounting frame is configured to retain a target wafer. The second wafer-mounting frame is configured to retain a masking wafer. The masking wafer includes a mask pattern made up of a number of openings passing through the masking wafer to correspond to a predetermined deposition pattern to be formed on the target wafer. A deposition chamber is configured to receive the first and second wafer-mounting frames, when the first and second wafer-mounting frames are clamped together to retain the target wafer and the masking wafer. The deposition chamber includes a material deposition source configured to deposit material from the material deposition source through the number of openings in the mask pattern to form the material in the predetermined deposition pattern on the target wafer.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 16, 2023
    Inventors: Ping-Yin Liu, Chia-Shiung Tsai, Xin-Hua Huang, Yu-Hsing Chang, Yeong-Jyh Lin
  • Patent number: 11818944
    Abstract: The present disclosure relates to a processing tool that includes a first wafer-mounting frame and a second wafer-mounting frame. The first wafer-mounting frame is configured to retain a target wafer. The second wafer-mounting frame is configured to retain a masking wafer. The masking wafer includes a mask pattern made up of a number of openings passing through the masking wafer to correspond to a predetermined deposition pattern to be formed on the target wafer. A deposition chamber is configured to receive the first and second wafer-mounting frames, when the first and second wafer-mounting frames are clamped together to retain the target wafer and the masking wafer. The deposition chamber includes a material deposition source configured to deposit material from the material deposition source through the number of openings in the mask pattern to form the material in the predetermined deposition pattern on the target wafer.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: November 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Yin Liu, Chia-Shiung Tsai, Xin-Hua Huang, Yu-Hsing Chang, Yeong-Jyh Lin
  • Publication number: 20230290714
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first redistribution structure, a packaged device and a second redistribution structure. The packaged device is on a first side of the first redistribution structure and the second redistribution structure is on a second side of the first redistribution structure. An encapsulant is on the second side of the first redistribution structure and laterally around the second redistribution structure, wherein the encapsulant covers a periphery of the second redistribution structure such that an uncovered surface of the second redistribution structure is defined.
    Type: Application
    Filed: March 14, 2022
    Publication date: September 14, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Yin Hsieh, Chih-Chien Pan, Li-Hui Cheng
  • Publication number: 20230290650
    Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a semiconductor die, conductive through vias, an insulating encapsulant, and a redistribution structure. The conductive through vias are electrically coupled to the semiconductor die. The insulating encapsulant laterally encapsulates the semiconductor die and the conductive through vias, wherein the insulating encapsulant has a recess ring surrounding the semiconductor die, the conductive through vias are located under the recess ring, and a vertical projection of each of the conductive through vias overlaps with a vertical projection of the recess ring. The redistribution structure is electrically connected to the semiconductor die and the conductive through vias.
    Type: Application
    Filed: May 22, 2023
    Publication date: September 14, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Hui Cheng, Szu-Wei Lu, Ping-Yin Hsieh, Chih-Hao Chen