Abstract: An integrated circuit generating a driving signal to a load according to an input voltage and including an impedance switching unit, a first protection unit, a first detection unit and a control unit is disclosed. The impedance switching unit takes the input voltage as the driving signal according to a control signal. The first protection unit generates a first detection signal when a current passing through the impedance switching unit is higher than a predetermined current. The first detection unit detects a voltage of the impedance switching unit to generate a detection result. The control unit controls the control signal according to the first detection signal.

Abstract: A power management circuit is provided. The power management circuit includes a power switch, a current/voltage detector, a current setting unit, and a control unit. The power switch is coupled to a power supply of the computer system. When the power switch is turned on, it supplies an output current and an output voltage of the power supply to an external device. The current/voltage detector detects the magnitudes of the output current and the output voltage. The current setting unit sets a plurality of current thresholds. When the computer system is in a power-saving state and when the output current is greater than a first current threshold and smaller than a second current threshold or the output voltage is smaller than a first voltage threshold and larger than a second voltage threshold, the control unit issues a notification signal to execute a predetermined operation on the power supply.

Abstract: A connector is provided. In one embodiment, the connector conforms to a data communication standard, and is connected to a cable, and comprises a contact opening and a control chip. The contact opening comprises a plurality of first contacts on a first side for performing a data communication process, and a plurality of second contacts on a second side for performing a rapid charging process. The control chip is coupled between the contact opening and the cable, and couples the second contacts to a downstream power port of the cable when the second contacts of the contact opening is coupled to a host connector of a host.

Abstract: Boot systems and methods are provided. The boot system includes an IO (Input/Output) chip, a memory device, and a BIOS (Basic Input/Output System). The memory device is coupled to the IO chip, and includes at least a rescue OS (Operating System). The BIOS reads the rescue OS from the memory device via the IO chip, and boots an electronic device based on the rescue OS.

Abstract: Boot systems and methods are provided. The boot system includes an IO (Input/Output) chip, a memory device, and a BIOS (Basic Input/Output System). The memory device is coupled to the IO chip, and includes at least a rescue OS (Operating System). The BIOS reads the rescue OS from the memory device via the IO chip, and boots an electronic device based on the rescue OS.

Abstract: Boot systems and methods are provided. The boot system includes an IO (Input/Output) chip, a memory device, and a BIOS (Basic Input/Output System). The memory device is coupled to the IO chip, and includes at least a rescue OS (Operating System). The BIOS reads the rescue OS from the memory device via the IO chip, and boots an electronic device based on the rescue OS.

Abstract: Boot systems and methods are provided. The boot system includes an IO (Input/Output) chip, a memory device, and a BIOS (Basic Input/Output System). The memory device is coupled to the IO chip, and includes at least a rescue OS (Operating System). The BIOS reads the rescue OS from the memory device via the IO chip, and boots an electronic device based on the rescue OS.

Abstract: A current limit protection apparatus and a method for current limit protection are provided. The current limit protection apparatus includes a MOS transistor, a current detecting unit, and a current limit circuit. Two source/drain of the MOS transistor are used for receiving a first-voltage and outputting a second-voltage respectively. A gate of the MOS transistor is used for receiving a gate driving signal to determine a conducting current of the MOS transistor. The current detecting unit is used for detecting the conducting current, so as to generate a detecting result. The current limit circuit has a plurality of current threshold values. The current limit circuit selects one of the current threshold values according to an indicating signal and generates the gate driving signal according to a difference between the selected current threshold value and the detecting result.

Abstract: A current limit protection apparatus and a method for current limit protection are provided. The current limit protection apparatus includes a MOS transistor, a current detecting unit, and a current limit circuit. Two source/drain of the MOS transistor are used for receiving a first-voltage and outputting a second-voltage respectively. A gate of the MOS transistor is used for receiving a gate driving signal to determine a conducting current of the MOS transistor. The current detecting unit is used for detecting the conducting current, so as to generate a detecting result. The current limit circuit has a plurality of current threshold values. The current limit circuit selects one of the current threshold values according to an indicating signal and generates the gate driving signal according to a difference between the selected current threshold value and the detecting result.

Abstract: A method for updating a firmware of a memory card is provided. The method includes: first, starting the memory card; then, determining whether there is a new firmware code or not in the nonvolatile memory; if it is determined that there is a new firmware code in the nonvolatile memory, then determining whether the new firmware code has been updated; if it is determined that the new firmware code has not been updated yet, then performing the firmware updating, and then performing the general operating procedure of the memory card. Therefore, instead of returning back to the memory card manufacturer, the user can conveniently update the memory card with a PC or a card reader.

Abstract: A USB host system includes a core logic having a host controller and a first root hub coupled thereto, a second root hub external to the core logic and coupled to the first root hub via a mapping interface, and a plurality of USB ports coupled to the second root hub, each of the USB ports adapted to couple an external USB device.

Abstract: A USB device is coupled to a first USB communication line and a second USB communication line. Separate first and second paths are created between an external device and a controller in the USB device, with both paths including the first and second USB communication lines. The USB device detects whether a USB connection exists over the first and second USB communication lines. If a USB connection exists over the first and second USB communication lines, USB communication is routed via the first path. Otherwise, testing communication is routed via the second path. The external device can be either a USB host or a testing unit.

Abstract: A monitor comprising two-way (plug and play) interface. A two-way interface is added in the monitor to achieve the function of mutual communication between a host hardware and monitor. Using the two-way interface, the specification data parameters are transferred to the host hardware, so that the host hardware can easily obtain the specification data parameters. Furthermore, the host hardware can send the parameters to the monitor controller to adjust the image data that meet the specification of the monitor to achieve the function and objective of plug-in of the monitor.

Abstract: An apparatus for canceling noise in a PC environment includes a receiver positioned inside the computer case that inputs noise inside the computer case, a processor coupled to the receiver and having a waveform generation device that generates a cancellation waveform that is inverse to the waveform of the input noise, and a speaker coupled to the processor for broadcasting the cancellation waveform. A method for canceling noise in a PC environment includes inputting a noise, determining a cyclical waveform that is representative of the noise, generating a cancellation waveform that is the reverse of the cyclical waveform, and mixing the sound from the cancellation waveform with the noise.

Abstract: A USB host system includes a core logic having a host controller and a first root hub coupled thereto, a second root hub external to the core logic and coupled to the first root hub via a mapping interface, and a plurality of USB ports coupled to the second root hub, each of the USB ports adapted to couple an external USB device.

Abstract: A method for selecting a wireless data transmitter to convey digital data from a first device to a second device. The first device has a transmitter and the second device has a receiver. A sole authentication number is assigned to the first device. A signal including the authentication number is conveyed from the transmitter of the first device and a login number corresponding to the authentication number is displayed on the second device when the receiver of the second device locates the signal. The login number is input into the first device, and the login number is then conveyed from the transmitter to the receiver such that the digital data from the first device is received by the second device.

Abstract: A USB device is coupled to a first USB communication line and a second USB communication line. Separate first and second paths are created between an external device and a controller in the USB device, with both paths including the first and second USB communication lines. The USB device detects whether a USB connection exists over the first and second USB communication lines. If a USB connection exists over the first and second USB communication lines, USB communication is routed via the first path. Otherwise, testing communication is routed via the second path. The external device can be either a USB host or a testing unit.