Abstract: A digital compute-in-memory (DCIM) system includes a first DCIM macro. The first DCIM macro includes a first memory cell array and a first arithmetic logic unit (ALU). The first memory cell array has N rows that are configured to store weight data of a neural network in a single weight data download session, wherein N is a positive integer not smaller than two. The first ALU is configured to receive a first activation input, and perform convolution operations upon the first activation input and a single row of weight data selected from the N rows of the first memory cell array to generate first convolution outputs.

Abstract: A digital compute-in-memory (DCIM) macro includes a memory cell array and an arithmetic logic unit (ALU). The memory cell array stores weight data of a neural network. The ALU receives parallel bits of a same input channel in an activation input, and generates a convolution computation output of the parallel bits and target weight data in the memory cell array.

Abstract: An image processing circuit performs super-resolution (SR) operations. The image processing circuit includes memory to store multiple parameter sets of multiple artificial intelligence (AI) models. The image processing circuit further includes an image guidance module, a parameter decision module, and an SR engine. The image guidance module operates to detect a representative feature in an image sequence including a current frame and past frames within a time window. The parameter decision module operates to adjust parameters of one or more AI models based on a measurement of the representative feature. The SR engine operates to process the current frame using the one or more AI models with the adjusted parameters to thereby generate a high-resolution image for display.

Abstract: A system receives a neural network model that includes asymmetric operations. Each asymmetric operation includes one or more fixed-point operands that are asymmetrically-quantized from corresponding floating-point operands. The system compiles a given asymmetric operation of the neural network model into a symmetric operation that includes a combined bias value. A compiler computes the combined bias value is a constant by merging at least zero points of input and output of the given asymmetric operation. The system then generates a symmetric neural network model including the symmetric operation for inference hardware to execute in fixed-point arithmetic.

Abstract: An image processing apparatus includes a super-resolution (SR) circuit and a resizer circuit. The SR circuit performs an SR operation upon a first image to generate a second image, wherein a resolution of the second image is not lower than a resolution of the first image, and the SR operation is based, at least in part, on one or more artificial intelligence (AI) models. The resizer circuit performs a resize operation upon the second image to generate a third image, wherein a resolution of the third image is not lower than the resolution of the second image, and no AI model is involved in the resize operation.

Abstract: An image processing circuit performs super-resolution (SR) operations. The image processing circuit includes memory to store multiple parameter sets of multiple artificial intelligent (AI) models. The image processing circuit further includes an image guidance module, a parameter decision module, and an SR engine. The image guidance module operates to detect a representative feature in an image sequence including a current frame and past frames within a time window. The parameter decision module operates to adjust parameters of one or more AI models based on a measurement of the representative feature. The SR engine operates to process the current frame using the one or more AI models with the adjusted parameters to thereby generate a high-resolution image for display.

Abstract: A protective film includes a non-adhesion layer and adhesion layer, and the non-adhesion layer further includes a surface layer and middle layer, where the surface layer of the non-adhesion layer is formed from a blend of Homo-polypropylene(H-PP) and low density polyethylene(LDPE), the middle layer of the non-adhesion layer is formed from a blend of high density Polyethylene(HDPE) and LDPE among Polyethylene series, and the adhesion layer is formed from thermoplastic elastomer added with low hardness plastic material, allowing the protective film of the present invention not to yield melting and thus sticking issues easily, and ensuring that the protective film has a good attachment and unwinding nature on application.

Abstract: A solar energy module is provided and includes a substrate comprising at least one light diffusion layer and a plurality of light guiding layers adjacent to the light diffusion layer, and solar chips disposed on the lateral surfaces of the substrate. Solar light enters the substrate and is diffused by the light diffusion layer, and the diffused solar light is reflected by an interface of the light diffusion layer and the light guiding layer and is collected by the solar chips. A part of the solar light enters the light guiding layers and is reflected by the interface of the light guiding layers, and the reflected light is collected by the solar chips.

Abstract: A solar energy module is provided and includes a substrate comprising at least one light diffusion layer and a plurality of light guiding layers adjacent to the light diffusion layer, and solar chips disposed on the lateral surfaces of the substrate. Solar light enters the substrate and is diffused by the light diffusion layer, and the diffused solar light is reflected by an interface of the light diffusion layer and the light guiding layer and is collected by the solar chips. A part of the solar light enters the light guiding layers and is reflected by the interface of the light guiding layers, and the reflected light is collected by the solar chips.