Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer.

Abstract: Migration results in specific action requests to move data from a source system instance to a target system instance. Migration may consume many resources. In an effort to monitor migration effects on source and/or target performance, one or more traffic lights are determined to monitor utilization of resources of the source and/or target. Based on the one or more traffic lights, migration is dynamically throttled. The one or more traffic light may be assigned a status based on how the migration affects performance of another data operation which may be contemporaneously operating on either the source and/or the target.

Abstract: Migration results in specific action requests to move data from a source system instance to a target system instance. Migration may consume many resources. In an effort to monitor migration effects on source and/or target performance, one or more traffic lights are determined to monitor utilization of resources of the source and/or target. Based on the one or more traffic lights, migration is dynamically throttled. The one or more traffic light may be assigned a status based on how the migration affects performance of another data operation which may be contemporaneously operating on either the source and/or the target.

Abstract: Provided are a method for photovoltaic module fault diagnosis, an edge calculation processing device and an inverter. Firstly, multiple module-level power electronic devices are controlled to perform IV scanning on photovoltaic modules connected to the module-level power electronic devices respectively and IV curves of the photovoltaic modules are obtained by the module-level power electronic devices respectively. Secondly, an IV curve satisfying a condition is selected from the IV curves of the photovoltaic modules as a reference curve. Thirdly, each of remaining IV curves in the IV curves of the photovoltaic modules other than the reference curve is compared with the reference curve, to generate comparison results. Finally, a fault diagnosis result for each of the photovoltaic modules is generated based on the comparison results.

Abstract: Migration results in specific action requests to move data from a source system instance to a target system instance. Migration may consume many resources. In an effort to monitor migration effects on source and/or target performance, one or more traffic lights are determined to monitor utilization of resources of the source and/or target. Based on the one or more traffic lights, migration is dynamically throttled. The one or more traffic light may be assigned a status based on how the migration affects performance of another data operation which may be contemporaneously operating on either the source and/or the target.

Abstract: Migration results in specific action requests to move data from a source system instance to a target system instance. Migration may consume many resources. In an effort to monitor migration effects on source and/or target performance, one or more traffic lights are determined to monitor utilization of resources of the source and/or target. Based on the one or more traffic lights, migration is dynamically throttled. The one or more traffic light may be assigned a status based on how the migration affects performance of another data operation which may be contemporaneously operating on either the source and/or the target.

Abstract: The invention discloses a method and a device for identifying pathological pictures, wherein the method comprises: obtaining sample data including a positive sample that is a pathological picture of malignant lesion and a negative sample that is a picture of normal tissue or a pathological picture of benign lesion, with a lesion area marked on the pathological picture of a malignant lesion; dividing the sample data into a training set and a testing set; training a deep neural network model using the training set; testing a trained deep neural network model using the testing set; adjusting parameters of the trained deep neural network model according to a testing result; identifying the pathological picture using the trained deep neural network model. The invention can improve the efficiency and accuracy of pathological picture identification.

Abstract: Provided are a method for photovoltaic module fault diagnosis, an edge calculation processing device and an inverter. Firstly, multiple module-level power electronic devices are controlled to perform IV scanning on photovoltaic modules connected to the module-level power electronic devices respectively and IV curves of the photovoltaic modules are obtained by the module-level power electronic devices respectively. Secondly, an IV curve satisfying a condition is selected from the IV curves of the photovoltaic modules as a reference curve. Thirdly, each of remaining IV curves in the IV curves of the photovoltaic modules other than the reference curve is compared with the reference curve, to generate comparison results. Finally, a fault diagnosis result for each of the photovoltaic modules is generated based on the comparison results.

Abstract: The invention discloses a method and a device for identifying pathological pictures, wherein the method comprises: obtaining sample data including a positive sample that is a pathological picture of malignant lesion and a negative sample that is a picture of normal tissue or a pathological picture of benign lesion, with a lesion area marked on the pathological picture of a malignant lesion; dividing the sample data into a training set and a testing set; training a deep neural network model using the training set; testing a trained deep neural network model using the testing set; adjusting parameters of the trained deep neural network model according to a testing result; identifying the pathological picture using the trained deep neural network model. The invention can improve the efficiency and accuracy of pathological picture identification.

Abstract: An adjustable dental implant comprises an implant body, a connecting structure, and two wings. The implant body comprises a fixture and an abutment. The fixture comprises a top, a bottom, a peripheral surface connected between the top and the bottom, and a joining portion formed on the peripheral surface. The abutment is set on the top of the fixture. The connecting structure is set between the fixture and the abutment. The wings are pivotally connected with two opposite sides of the connecting structure. Or, one of the wings is pivotally connected with the connecting structure, and the other wing is fixed with the connecting structure. The wing or the wings may be adjusted to fit the surface of the cortical bone. Dental posts are allowed to penetrate the alveolar bone entirely to secure the fixture.

Abstract: An adjustable dental implant comprises an implant body, a connecting structure, and two wings. The implant body comprises a fixture and an abutment. The fixture comprises a top, a bottom, a peripheral surface connected between the top and the bottom, and a joining portion formed on the peripheral surface. The abutment is set on the top of the fixture. The connecting structure is set between the fixture and the abutment. The wings are pivotally connected with two opposite sides of the connecting structure. Or, one of the wings is pivotally connected with the connecting structure, and the other wing is fixed with the connecting structure. The wing or the wings may be adjusted to fit the surface of the cortical bone. Dental posts are allowed to penetrate the alveolar bone entirely to secure the fixture.

Abstract: The present invention relates to a nano-graphite plate structure with N graphene layers stacked together, where N is 30 to 300. The nanometer nano-graphite structure has a tap density of 0.1 g/cm3 to 0.01 cm3, a thickness of 10 nm to 100 nm, and a lateral dimension of 1 ?m to 100 ?m. The ratio of the lateral dimension to the thickness is between 10 and 10,000. The oxygen content is less than 3 wt %, and the carbon content is larger than 95 wt %. The nano-graphite plate structure has both the excellent features of the graphene and the original advantages of easy processability of the natural graphite so as to be broadly used in various application fields.

Abstract: A method for manufacturing nano-graphene sheets, includes: intercalating and oxidizing a graphite material to form a graphite oxide by mixing the graphite material with an intercalation agent and oxidant; contacting the graphite oxide with a heat source to thermally flake the graphite oxide to nano-graphite sheets; suspending the nano-graphite sheets in a liquid medium and applying a mechanical shear force larger than 5,000 psi to mechanically flake the nano-graphite sheets for reducing the lateral size and thickness to form a nano-graphene suspension solution; separating the nano-graphene sheets from the nano-graphene suspension solution and drying the nano-graphene sheets; and finally reducing and heat treating the nano-graphene sheets to lower the oxygen content to less than 3 wt % and decrease the crystal defects.

Abstract: The present invention relates to a nano-graphite plate structure with N graphene layers stacked together, where N is 30 to 300. The nanometer nano-graphite structure has a tap density of 0.1 g/cm3 to 0.01 cm3, a thickness of 10 nm to 100 nm, and a lateral dimension of 1 ?m to 100 ?m. The ratio of the lateral dimension to the thickness is between 10 and 10,000. The oxygen content is less than 3 wt %, and the carbon content is larger than 95 wt %. The nano-graphite plate structure has both the excellent features of the graphene and the original advantages of easy processability of the natural graphite so as to be broadly used in various application fields.

Abstract: An HCG to HDL translation method, which can automatically generate VHDL codes. The method reads a hardware component graph (HCG) to find a start node and obtain a corresponding hardware component subgraph of the start node, analyzes all information of the start node to thereby add input and output components and generate a VHDL entity, determines types on all nodes of the hardware component, graph to thereby generate corresponding VHDL components and write associated information in a VHDL architecture, generates corresponding signal connections of VHDL components in accordance with edges of the hardware component graph, and outputs the VHDL entity and architecture to a file in a text form.

Abstract: A process of automatically translating a high level programming language into an extended activity diagram (EAD), which can translate source codes coded by the high level programming language into a corresponding activity diagram (AD) before the high level language is translated into a hardware description language (HDL). The process adds a new translation rule in a compiler and modifies the AD specification of a unified modeling language (UML) to accordingly translate the source codes into the AD and present the programming logic and executing flow of the source codes in a visualization form. In addition, the process can translate the high level programming language into a unified format for representation, and the AD can benefit simulation and requirement in a following HDL translation.

Abstract: A process of automatically translating an extended activity diagram (EAD) into a hardware component graph (HCG).