Patents by Inventor Ping-Chang Lin

Ping-Chang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11982936
    Abstract: A method of fabricating a photomask includes selectively exposing portions of a photomask blank to radiation to change an optical property of the portions of the photomask blank exposed to the radiation, thereby forming a pattern of exposed portions of the photomask blank and unexposed portions of the photomask blank. The pattern corresponds to a pattern of semiconductor device features.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsin-Chang Lee, Ping-Hsun Lin, Yen-Cheng Ho, Chih-Cheng Lin, Chia-Jen Chen
  • Publication number: 20240094625
    Abstract: A method of making a semiconductor device includes forming at least one fiducial mark on a photomask. The method further includes defining a pattern including a plurality of sub-patterns on the photomask in a pattern region. The defining the pattern includes defining a first sub-pattern of the plurality of sub-patterns having a first spacing from a second sub-pattern of the plurality of sub-patterns, wherein the first spacing is different from a second spacing between the second sub-pattern and a third sub-pattern of the plurality of sub-patterns.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Hsin-Chang LEE, Ping-Hsun LIN, Chih-Cheng LIN, Chia-Jen CHEN
  • Publication number: 20240077804
    Abstract: A method includes forming a test pattern and a reference pattern in an absorption layer of a photomask structure. The test pattern has a first trench and a second trench, the reference pattern has a third trench and a fourth trench, the test pattern and the reference pattern have substantially the same dimension in a top view, and the second trench is deeper than the first trench, the third trench, and the fourth trench. The method further includes emitting a light beam to the test pattern to obtain a first interference pattern reflected from the test pattern, emitting the light beam to the reference pattern to obtain a second interference pattern reflected from the reference pattern; and comparing the first interference pattern with the second interference pattern to obtain a measured complex refractive index of the absorption layer.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ping-Hsun LIN, Chien-Cheng CHEN, Shih Ju HUANG, Pei-Cheng HSU, Ta-Cheng LIEN, Hsin-Chang LEE
  • Publication number: 20240069431
    Abstract: In a method of manufacturing an attenuated phase shift mask, a photo resist pattern is formed over a mask blank. The mask blank includes a transparent substrate, an etch stop layer on the transparent substrate, a phase shift material layer on the etch stop layer, a hard mask layer on the phase shift material layer and an intermediate layer on the hard mask layer. The intermediate layer is patterned by using the photo resist pattern as an etching mask, the hard mask layer is patterned by using the patterned intermediate layer as an etching mask, and the phase shift material layer is patterned by using the patterned hard mask layer as an etching mask. The intermediate layer includes at least one of a transition metal, a transition metal alloy, or a silicon containing material, and the hard mask layer is made of a different material than the intermediate layer.
    Type: Application
    Filed: February 16, 2023
    Publication date: February 29, 2024
    Inventors: Wei-Che HSIEH, Chien-Cheng Chen, Ping-Hsun Lin, Ta-Cheng Lien, Hsin-Chang Lee
  • Patent number: 9780085
    Abstract: An electronic static discharge protection apparatus provided. A plurality of ESD circuits serially coupled between a pad and a internal circuit, a first stage ESD circuit includes a ESD element directly coupled to the pad, and a last stage ESD circuit includes an inductive element directly coupled to the internal circuit, so as to improve electronic discharge protecting ability of the ESD protection apparatus and increase circuit operation bandwidth without signal loss attenuation.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: October 3, 2017
    Assignee: Novatek Microelectronics Corp.
    Inventors: Rong-Kun Chang, Jie-Ting Chen, Chun-Yu Lin, Ming-Dou Ker, Tzu-Chien Tzeng, Ping-Chang Lin