Patents by Inventor Pinghui Li
Pinghui Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230144064Abstract: Disclosed are a system and method for automatically and systematically generating device-based design rules and corresponding device-based design rule checking (DRC) codes. In the system and method, design rules associated with specific devices are generated based on at least one table of related data (e.g., maturity status information, restriction status information, etc.) for different devices. Based on the design rules and on unique definitions for the specific devices, design rule checking (DRC) codes associated with the specific devices are generated. By using this approach, comprehensive and accurate device-based design rules and corresponding device-based DRC codes can be quickly generated to ensure acceptable product reliability and yield. Furthermore, processes used to generate the device-based DRC codes can be iteratively repeated (e.g.Type: ApplicationFiled: November 5, 2021Publication date: May 11, 2023Applicant: GlobalFoundries Singapore Pte. Ltd.Inventors: Shu Zhong, Ming Zhu, Pinghui Li, Yiang Aun Nga
-
Patent number: 11545570Abstract: The present disclosure generally to semiconductor devices, and more particularly to semiconductor devices having high-voltage transistors integrated on a semiconductor-on-insulator substrate and methods of forming the same. The present disclosure provides a semiconductor device including a semiconductor-on-insulator (SOI) substrate having a semiconductor layer, a bulk substrate and an insulating layer between the semiconductor layer and the bulk substrate, a source region and a drain region disposed on the bulk substrate, an isolation structure extending through the insulating layer and the semiconductor layer and terminates in the bulk substrate, and a gate structure between the source region and the drain region, the gate structure is disposed on the semiconductor layer.Type: GrantFiled: January 8, 2020Date of Patent: January 3, 2023Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Pinghui Li, Handoko Linewih, Darin Arthur Chan, Ruchil Kumar Jain
-
Publication number: 20210210630Abstract: The present disclosure generally to semiconductor devices, and more particularly to semiconductor devices having high-voltage transistors integrated on a semiconductor-on-insulator substrate and methods of forming the same. The present disclosure provides a semiconductor device including a semiconductor-on-insulator (SOI) substrate having a semiconductor layer, a bulk substrate and an insulating layer between the semiconductor layer and the bulk substrate, a source region and a drain region disposed on the bulk substrate, an isolation structure extending through the insulating layer and the semiconductor layer and terminates in the bulk substrate, and a gate structure between the source region and the drain region, the gate structure is disposed on the semiconductor layer.Type: ApplicationFiled: January 8, 2020Publication date: July 8, 2021Inventors: PINGHUI LI, HANDOKO LINEWIH, DARIN ARTHUR CHAN, RUCHIL KUMAR JAIN
-
Patent number: 10978510Abstract: Methods of forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions and the resulting device are provided. Embodiments include providing an embedded MRAM layout with near-active-MRAM-cell periphery logic and far-outside-MRAM logic regions; forming a MTJ structure within the layout based on minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first and second metal layers; forming a high-density MTJ dummy structure in the near-active-MRAM-cell periphery logic region based on second minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer; and forming a low-density MTJ dummy structure in the far-outside-MRAM logic region based on third minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer.Type: GrantFiled: June 17, 2019Date of Patent: April 13, 2021Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Pinghui Li, Haiqing Zhou, Liying Zhang, Wanbing Yi, Ming Zhu, Danny Pak-Chum Shum, Darin Chan
-
Patent number: 10741552Abstract: Methods for preventing step-height difference of flash and logic gates in FinFET devices and related devices are provided. Embodiments include forming fins in flash and logic regions; recessing an oxide exposing an upper portion of the fins; forming an oxide liner over the upper portion in the flash region; forming a polysilicon gate over and perpendicular to the fins in both regions; removing the gate from the logic region and patterning the gate in the flash region forming a separate gate over each fin; forming an ONO layer over the gates in the flash region; forming a second polysilicon gate over and perpendicular to the fins in both regions; planarizing the second polysilicon gate exposing a portion of the ONO layer over the gates in the flash region; forming and patterning a hardmask, exposing STI regions between the flash and logic regions; and forming an ILD over the STI regions.Type: GrantFiled: July 19, 2018Date of Patent: August 11, 2020Assignee: GLOBALFOUNDERS SINGAPORE PTE. LTD.Inventors: Ming Zhu, Pinghui Li, Su Yi Susan Yeow, Yiang Aun Nga, Danny Pak-Chum Shum, Eng Huat Toh
-
Publication number: 20190305041Abstract: Methods of forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions and the resulting device are provided. Embodiments include providing an embedded MRAM layout with near-active-MRAM-cell periphery logic and far-outside-MRAM logic regions; forming a MTJ structure within the layout based on minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first and second metal layers; forming a high-density MTJ dummy structure in the near-active-MRAM-cell periphery logic region based on second minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer; and forming a low-density MTJ dummy structure in the far-outside-MRAM logic region based on third minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer.Type: ApplicationFiled: June 17, 2019Publication date: October 3, 2019Inventors: Pinghui LI, Haiqing ZHOU, Liying ZHANG, Wanbing YI, Ming ZHU, Danny Pak-Chum SHUM, Darin CHAN
-
Patent number: 10411027Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a fin extending from the substrate. The fin includes a first and second fin sidewall, and a memory cell layer is adjacent to the first and second fin sidewalls. A first control gate is adjacent to the memory cell layer where the memory cell layer is between the first fin sidewall and the first control gate. A second control gate is also adjacent to the memory cell layer, where the memory cell layer is between the second fin sidewall and the second control gate. The first and second control gates are electrically isolated from each other.Type: GrantFiled: October 19, 2017Date of Patent: September 10, 2019Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Ming Zhu, Pinghui Li, Eng Huat Toh, Yiang Aun Nga, Danny Pak-Chum Shum
-
Patent number: 10381360Abstract: A method of forming a uniform WL over the MCEL region and resulting device are provided. Embodiments include providing a substrate having a MCEL region, a HV region and a logic region, separated by an isolation region; forming a plurality of CG stacks over the MCEL region, and a plurality of CG dummy stacks over the HV region and the logic region, respectively; forming first and second overlying polysilicon layers with a spacer therebetween, an EG and a WL on the MCEL region formed; planarizing the second polysilicon layer down to upper surface of the plurality of CG stacks and the plurality of CG dummy stacks; and removing portions of the second polysilicon layer in-between the plurality of CG stacks and around the plurality of CG dummy stacks.Type: GrantFiled: March 22, 2018Date of Patent: August 13, 2019Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Laiqiang Luo, Sen Mei, Fangxin Deng, Zhiqiang Teo, Fan Zhang, Pinghui Li, Haiqing Zhou, Xingyu Chen, Kin Leong Pey
-
Patent number: 10374005Abstract: Methods of forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions and the resulting device are provided. Embodiments include providing an embedded MRAM layout with near-active-MRAM-cell periphery logic and far-outside-MRAM logic regions; forming a MTJ structure within the layout based on minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first and second metal layers; forming a high-density MTJ dummy structure in the near-active-MRAM-cell periphery logic region based on second minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer; and forming a low-density MTJ dummy structure in the far-outside-MRAM logic region based on third minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer.Type: GrantFiled: December 29, 2017Date of Patent: August 6, 2019Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Pinghui Li, Haiqing Zhou, Liying Zhang, Wanbing Yi, Ming Zhu, Danny Pak-Chum Shum, Darin Chan
-
Publication number: 20190206928Abstract: Methods of forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions and the resulting device are provided. Embodiments include providing an embedded MRAIVI layout with near-active-MRAM-cell periphery logic and far-outside-MRAM logic regions; forming a MTJ structure within the layout based on minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first and second metal layers; forming a high-density MTJ dummy structure in the near-active-MRAM-cell periphery logic region based on second minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer; and forming a low-density MTJ dummy structure in the far-outside-MRAM logic region based on third minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer.Type: ApplicationFiled: December 29, 2017Publication date: July 4, 2019Inventors: Pinghui LI, Haiqing ZHOU, Liying ZHANG, Wanbing YI, Ming ZHU, Danny Pak-Chum SHUM, Darin CHAN
-
Publication number: 20190123059Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a fin extending from the substrate. The fin includes a first and second fin sidewall, and a memory cell layer is adjacent to the first and second fin sidewalls. A first control gate is adjacent to the memory cell layer where the memory cell layer is between the first fin sidewall and the first control gate. A second control gate is also adjacent to the memory cell layer, where the memory cell layer is between the second fin sidewall and the second control gate. The first and second control gates are electrically isolated from each other.Type: ApplicationFiled: October 19, 2017Publication date: April 25, 2019Inventors: Ming Zhu, Pinghui Li, Eng Huat Toh, Yiang Aun Nga, Danny Pak-Chum Shum
-
Patent number: 10211336Abstract: LDMOS transistor structures and integrated circuits including LDMOS transistor structures are provided. An exemplary integrated circuit including an LDMOS transistor structure includes a substrate including a first region and a second region. The substrate includes a bulk layer and, in the second region, an insulator layer overlying the bulk layer and a semiconductor layer overlying the insulator layer. The integrated circuit further includes a gate structure overlying the semiconductor layer. A channel region is formed in the semiconductor layer under the gate structure. The integrated circuit also includes a well contact region on the bulk layer in the first region, a source region overlying the substrate, and a drain region overlying the substrate. A drift region is located between the drain region and the gate structure.Type: GrantFiled: October 16, 2017Date of Patent: February 19, 2019Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Ming Zhu, Shi Ya Phyllis Lim, Pinghui Li, Yiang Aun Nga
-
Publication number: 20180374850Abstract: Methods for preventing step-height difference of flash and logic gates in FinFET devices and related devices are provided. Embodiments include forming fins in flash and logic regions; recessing an oxide exposing an upper portion of the fins; forming an oxide liner over the upper portion in the flash region; forming a polysilicon gate over and perpendicular to the fins in both regions; removing the gate from the logic region and patterning the gate in the flash region forming a separate gate over each fin; forming an ONO layer over the gates in the flash region; forming a second polysilicon gate over and perpendicular to the fins in both regions; planarizing the second polysilicon gate exposing a portion of the ONO layer over the gates in the flash region; forming and patterning a hardmask, exposing STI regions between the flash and logic regions; and forming an ILD over the STI regions.Type: ApplicationFiled: July 19, 2018Publication date: December 27, 2018Inventors: Ming ZHU, Pinghui LI, Su Yi Susan YEOW, Yiang Aun NGA, Danny Pak-Chum SHUM, Eng Huat TOH
-
Publication number: 20180374849Abstract: Methods for preventing step-height difference of flash and logic gates in FinFET devices and related devices are provided. Embodiments include forming fins in flash and logic regions; recessing an oxide exposing an upper portion of the fins; forming an oxide liner over the upper portion in the flash region; forming a polysilicon gate over and perpendicular to the fins in both regions; removing the gate from the logic region and patterning the gate in the flash region forming a separate gate over each fin; forming an ONO layer over the gates in the flash region; forming a second polysilicon gate over and perpendicular to the fins in both regions; planarizing the second polysilicon gate exposing a portion of the ONO layer over the gates in the flash region; forming and patterning a hardmask, exposing STI regions between the flash and logic regions; and forming an ILD over the STI regions.Type: ApplicationFiled: June 23, 2017Publication date: December 27, 2018Inventors: Ming ZHU, Pinghui LI, Su Yi Susan YEOW, Yiang Aun NGA, Danny Pak-Chum SHUM, Eng Huat TOH
-
Patent number: 10163901Abstract: Methods for preventing step-height difference of flash and logic gates in FinFET devices and related devices are provided. Embodiments include forming fins in flash and logic regions; recessing an oxide exposing an upper portion of the fins; forming an oxide liner over the upper portion in the flash region; forming a polysilicon gate over and perpendicular to the fins in both regions; removing the gate from the logic region and patterning the gate in the flash region forming a separate gate over each fin; forming an ONO layer over the gates in the flash region; forming a second polysilicon gate over and perpendicular to the fins in both regions; planarizing the second polysilicon gate exposing a portion of the ONO layer over the gates in the flash region; forming and patterning a hardmask, exposing STI regions between the flash and logic regions; and forming an ILD over the STI regions.Type: GrantFiled: June 23, 2017Date of Patent: December 25, 2018Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Ming Zhu, Pinghui Li, Su Yi Susan Yeow, Yiang Aun Nga, Danny Pak-Chum Shum, Eng Huat Toh
-
Patent number: 10109638Abstract: A semiconductor device with embedded non-volatile memory (eNVM) is described. The device is formed on a silicon-on-insulator (SOI) substrate, such as a fully depleted SOI (FDSOI) substrate. The substrate includes a SOI region and a hybrid region. The SOI region includes the surface substrate, BOX and bulk substrate while the hybrid region includes only the bulk substrate. NVM and high voltage (HV) transistors are disposed in the hybrid region while a logic and radio frequency (RF) transistors are disposed in the SOI region. The gates of the various transistors have about coplanar top surfaces. As such, the hybrid region compensates for height differential of transistors, enabling transistors to have about coplanar top surfaces. In addition, the hybrid region enables transistors which suffer from floating body effects to be disposed therein.Type: GrantFiled: October 23, 2017Date of Patent: October 23, 2018Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Ming Zhu, Pinghui Li, Danny Shum, Fan Zhang, Yiang Aun Nga
-
Publication number: 20180090505Abstract: Methods of producing integrated circuits are provided. An exemplary method includes patterning a source line photoresist mask to overlie a source line area of a substrate while exposing a drain line area. The source line area is between a first and second memory cell and the drain line area is between the second and a third memory cell. A source line is formed in the source line area. A source line dielectric is concurrently formed overlying the source line while a drain line dielectric is formed overlying a drain line area. A drain line photoresist mask is patterned to overlie the source line in an active section while exposing the source line in a strap section, and while exposing the drain line area. The drain line dielectric is removed from over the drain line area while a thickness of the source line dielectric in the strap section is reduced.Type: ApplicationFiled: September 28, 2016Publication date: March 29, 2018Inventors: Laiqiang Luo, Yu Jin Eugene Kong, Daxiang Wang, Fan Zhang, Danny Pak-Chum Shum, Pinghui Li, Zhiqiang Teo, Juan Boon Tan, Soh Yun Siah, Pey Kin Leong
-
Patent number: 9929165Abstract: Methods of producing integrated circuits are provided. An exemplary method includes patterning a source line photoresist mask to overlie a source line area of a substrate while exposing a drain line area. The source line area is between a first and second memory cell and the drain line area is between the second and a third memory cell. A source line is formed in the source line area. A source line dielectric is concurrently formed overlying the source line while a drain line dielectric is formed overlying a drain line area. A drain line photoresist mask is patterned to overlie the source line in an active section while exposing the source line in a strap section, and while exposing the drain line area. The drain line dielectric is removed from over the drain line area while a thickness of the source line dielectric in the strap section is reduced.Type: GrantFiled: September 28, 2016Date of Patent: March 27, 2018Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Laiqiang Luo, Yu Jin Eugene Kong, Daxiang Wang, Fan Zhang, Danny Pak-Chum Shum, Pinghui Li, Zhiqiang Teo, Juan Boon Tan, Soh Yun Siah, Pey Kin Leong
-
Publication number: 20180053842Abstract: LDMOS transistor structures and integrated circuits including LDMOS transistor structures are provided. An exemplary integrated circuit including an LDMOS transistor structure includes a substrate including a first region and a second region. The substrate includes a bulk layer and, in the second region, an insulator layer overlying the bulk layer and a semiconductor layer overlying the insulator layer. The integrated circuit further includes a gate structure overlying the semiconductor layer. A channel region is formed in the semiconductor layer under the gate structure. The integrated circuit also includes a well contact region on the bulk layer in the first region, a source region overlying the substrate, and a drain region overlying the substrate. A drift region is located between the drain region and the gate structure.Type: ApplicationFiled: October 16, 2017Publication date: February 22, 2018Inventors: Ming Zhu, Shi Ya Phyllis Lim, Pinghui Li, Yiang Aun Nga
-
Patent number: 9825185Abstract: Integrated circuits and methods for fabricating integrated circuits with non-volatile memory structures are provided. An exemplary integrated circuit includes a semiconductor substrate having a central semiconductor-on-insulator (SOI) region between first and second non-SOI regions. The substrate includes a semiconductor base in the SOI region and the non-SOI regions, an insulator layer overlying the semiconductor base in the SOI region, and an upper semiconductor layer overlying the insulator layer in the SOI region. The integrated circuit further includes a first conductivity type well formed in the base in the first region and in a first portion of the SOI region, and a second conductivity type well formed in the base in the second region and in a second portion of the SOI region lateral of the first conductivity type well. Also, the integrated circuit includes a non-volatile memory device structure overlying the upper semiconductor layer in the SOI region.Type: GrantFiled: December 19, 2016Date of Patent: November 21, 2017Assignee: GLOBALFOUDNRIES SINGAPORE PTE. LTD.Inventors: Pinghui Li, Ming Zhu, Xinshu Cai, Fan Zhang, Danny Pak-Chum Shum, Darin Chan