Abstract: A circuit board assembly in a camera module for blocking unwanted light when images are captured includes a circuit board, a sensor, and an optical blocking body connecting the circuit board and the sensor. The circuit board includes a base board and a photomask. The photomask is arranged on a surface of the base board, the base board includes conductive circuit layers and dielectric layers, the conductive circuit layers and the dielectric layers are alternately arranged, the sensor being electronically connected to the conductive layers. The optical blocking body, the photomask, and the dielectric layers block ambient light entering the camera module other than through the lens assembly of the camera module.

Abstract: A fingerprint sensing system comprising a plurality of conductive selection lines; a plurality of conductive read-out lines crossing the selection lines; selection circuitry controllable to provide a selection signal on at least one selected selection line in the plurality of selection lines; a plurality of pixel elements formed at intersections between the selection lines and the read-out lines; current providing circuitry coupled to the read-out lines and controllable to generate a current pulse in at least one of the read-out lines when reading out a sensing signal from each of the pixel elements.

Abstract: A fingerprint sensing system comprising a plurality of conductive selection lines; a plurality of conductive read-out lines crossing the selection lines; selection circuitry controllable to provide a selection signal on at least one selected selection line in the plurality of selection lines; a plurality of pixel elements formed at intersections between the selection lines and the read-out lines; current providing circuitry coupled to the read-out lines and controllable to generate a current pulse in at least one of the read-out lines when reading out a sensing signal from each of the pixel elements.

Abstract: An operational amplifier includes a first output transistor and a second output transistor connected in series between two power nodes, the second output transistor having a semiconductor type opposite to the first output transistor, the first output transistor and the second output transistor being electrically coupled at an output node, and gates of the first output transistor and the second output transistor being connected to a first drive node and a second drive node respectively; and a decoupling capacitor circuit electrically connected between the first drive node and the second drive node.

Abstract: An operational amplifier includes a first output transistor and a second output transistor connected in series between two power nodes, the second output transistor having a semiconductor type opposite to the first output transistor, the first output transistor and the second output transistor being electrically coupled at an output node, and gates of the first output transistor and the second output transistor being connected to a first drive node and a second drive node respectively; and a decoupling capacitor circuit electrically connected between the first drive node and the second drive node.

Abstract: A capacitor includes a first transistor, a second transistor, and a control circuit. The first terminal of the first transistor is coupled to the first terminal of the capacitor. The first terminal of the second transistor is coupled to the second terminal of the capacitor. In a normal mode, the control circuit turns on the first transistor and the second transistor, the second terminal of the second transistor is coupled to the control terminal of the first transistor through the control circuit, and the control terminal of the second transistor is coupled to the second terminal of the first transistor through the control circuit. In a power saving mode, the control circuit turns off the first transistor and the second transistor.

Abstract: A capacitor includes a first transistor, a second transistor, and a control circuit. The first terminal of the first transistor is coupled to the first terminal of the capacitor. The first terminal of the second transistor is coupled to the second terminal of the capacitor. In a normal mode, the control circuit turns on the first transistor and the second transistor, the second terminal of the second transistor is coupled to the control terminal of the first transistor through the control circuit, and the control terminal of the second transistor is coupled to the second terminal of the first transistor through the control circuit. In a power saving mode, the control circuit turns off the first transistor and the second transistor.

Abstract: The present invention provides a voltage level shifter architecture applicable for positive and negative voltage shifting, in which a shielding circuit is configured to relax the voltage stress of the transistors in the input stage circuit, and a switching circuit is configured to avoid current leakage. In addition, designing the power domain(s) of the n-well P-type transistors in the voltage-level shifter makes the voltage-level shifter area-efficient and power-efficient or design-flexible and application-adaptive.