Abstract: The present application discloses a device variation extraction chip, including m MOS devices and one test key, where the test key has 2n pads; a drain of the (k(n?1)+i)-th MOS device is short-circuited with the i-th pad of the test key; a gate of the (k(n?1)+i)-th MOS device is short-circuited with the (n?1+i)-th pad of the test key; a source of each of the m MOS devices is short-circuited with the (2n?1)-th pad; a bulk of each of the m MOS devices is short-circuited with the 2n-th pad. The device variation extraction chip can save the chip area, save the test time, obtain a large amount of data, and improve the accuracy of the obtained device variation and device mismatch, without the addition of a photomask and process node steps.

Abstract: The present application discloses a method for making an 8-transistor 2-port static random access memory, wherein an N LDD process for 6 transistors in a chip memory area uses an N LDD mask and a P LDD mask of an original storage unit, and source and drain areas of an N transistor of a read port is opened for ion injection when LDD is performed for a logic device in a chip logic area to complete an N LDD process for the N transistor of the read port, so as to adjust a threshold voltage Vt and a source-drain breakthrough current Ids of the N transistor of the read port, thereby adjusting the read current and read speed for the read port without affecting the read/write balance for 6T SRAM inside a storage unit and without an extra mask or an increase in process steps.

Abstract: The present application discloses a device variation extraction chip, including m MOS devices and one test key, where the test key has 2n pads; a drain of the (k(n?1)+i)-th MOS device is short-circuited with the i-th pad of the test key; a gate of the (k(n?1)+i)-th MOS device is short-circuited with the (n?1+i)-th pad of the test key; a source of each of the m MOS devices is short-circuited with the (2n?1)-th pad; a bulk of each of the m MOS devices is short-circuited with the 2n-th pad. The device variation extraction chip can save the chip area, save the test time, obtain a large amount of data, and improve the accuracy of the obtained device variation and device mismatch, without the addition of a photomask and process node steps.

Abstract: The present application discloses a three-port SRAM circuit, which is formed by adding two read ports to a six-transistor single-port SRAM circuit. Storage states of a first node and a second node of the six-transistor single-port SRAM circuit are opposite, so that a third P-type transistor with a gate terminal thereof corresponding to the first node and a fifth N-type transistor with a gate terminal thereof corresponding to the second node can be on/off synchronously. When a sixth N-type transistor and a fourth P-type transistor are both on, a port C bit line and a port B bit line can be held/discharge synchronously, so as to facilitate a system operating a peripheral circuit simultaneously when reading ports B and C at high speeds.

Abstract: The present application discloses a dual-port SRAM having two ports. On a layout, pass gates connecting to the two ports are disposed near pull down transistors of corresponding memory nodes. A cell layout structure of the SRAM cell structure is centrosymmetric. In a first subunit layout structure, a pass gate and a first pull down transistor share the same active region, and an active region of the other pull down transistor is disposed between active regions of the first pull down transistor and a first pull up transistor. The present application improves the symmetry of read paths of the two memory nodes from two ports thus the symmetry of read currents, therefore the variation of the electrical performance of PMOS transistors is reduced and the stability of the electrical performance of the PMOS transistors is improved.

Abstract: The present application discloses a dual-port SRAM having two ports. On a layout, pass gates connecting to the two ports are disposed near pull down transistors of corresponding memory nodes. A cell layout structure of the SRAM cell structure is centrosymmetric. In a first subunit layout structure, a pass gate and a first pull down transistor share the same active region, and an active region of the other pull down transistor is disposed between active regions of the first pull down transistor and a first pull up transistor. The present application improves the symmetry of read paths of the two memory nodes from two ports thus the symmetry of read currents, therefore the variation of the electrical performance of PMOS transistors is reduced and the stability of the electrical performance of the PMOS transistors is improved.

Abstract: The memory comprises a first pass gate transistor, a second pass gate transistor, a third pass gate transistor, and a fourth pass gate transistor. On-resistance of the second pass gate transistor is smaller than that of the first pass gate transistor, so that first read current flowing from a first read/write port of a first group of read/write dual ports is equal to second read current flowing from a second read/write port of the first group of read/write dual port. On-resistance of the fourth pass gate transistor is smaller than that of the third pass gate transistor, so that third read current flowing from a first read/write port of a second group of read/write dual ports is equal to fourth read current flowing from a second read/write port of the second group of read/write dual port.

Abstract: The memory comprises a first pass gate transistor, a second pass gate transistor, a third pass gate transistor, and a fourth pass gate transistor. On-resistance of the second pass gate transistor is smaller than that of the first pass gate transistor, so that first read current flowing from a first read/write port of a first group of read/write dual ports is equal to second read current flowing from a second read/write port of the first group of read/write dual port. On-resistance of the fourth pass gate transistor is smaller than that of the third pass gate transistor, so that third read current flowing from a first read/write port of a second group of read/write dual ports is equal to fourth read current flowing from a second read/write port of the second group of read/write dual port.

Abstract: The present disclosure provides a testing method for reading current of static random access memory, the method comprising: for each basic static random access memory cell, coupling a gate of a first pull-down transistor to a first bit line; setting a word line and the first bit line at a high potential; and sensing current of the first bit line. The testing method provided in the present disclosure can also be applied to static random access memory cells arranged in matrices, so as to efficiently complete the tests for the reading current of the static random access memory in batches.

Abstract: The present disclosure provides a testing method for reading current of static random access memory, the method comprising: for each basic static random access memory cell, coupling a gate of a first pull-down transistor to a first bit line; setting a word line and the first bit line at a high potential; and sensing current of the first bit line. The testing method provided in the present disclosure can also be applied to static random access memory cells arranged in matrices, so as to efficiently complete the tests for the reading current of the static random access memory in batches.