Abstract: The present invention discloses an organic light emitting diode flexible array substrate including a displaying region, a folding region adjacent to the displaying region, a flexible substrate, barrier layer, a buffer layer, a polycrystalline layer stacked together, a first insulation layer disposed on the buffer layer and covering the polycrystalline layer, a first metal layer, a second metal layer, and a third metal layer. Folding signal lines are formed on a portion of the second metal layer in the folding region. Folding signal lines are formed on a portion of the third metal layer in the folding region. Double folding signal lines of the second metal layer and third metal layer drastically increase reliability and lifespan of the signal lines in the folding region.

Abstract: Provided in the present application a display panel, comprising a substrate, wherein the substrate comprises a display area, an aperture area, located in the display area; and a partition area, surrounding the aperture area and provided with at least one partition ring disposed around the aperture area, wherein a partition groove is disposed on at least one side of the partition ring, wherein the partition groove comprises a third partition groove, a first partition groove, and a second partition groove that are disposed on a side along a first direction away from the substrate in sequence, and communicated with each other, and the first partition groove is used to separate an organic material layer on a side wall of the second partition groove from another organic material layer on a side of the third partition groove.

Abstract: An array substrate and manufacturing method thereof are provided. The method includes the following steps: fabricating an array substrate, in which a non-display portion at a side of a display portion of the array substrate is provided with a curved with region. The display portion includes an inorganic film layer and a thin film transistor, and the non-display portion includes a groove corresponding to the curved region and penetrating through the inorganic film layer. The method then includes fabricating a first planarization layer on the inorganic film layer, in which the first planarization layer fills into the groove and the first planarization layer is patterned to form via-holes in the planarization layer, and fabricating a metal layer on the first planarization layer so as to form an auxiliary electrode connecting with the thin film transistor.

Abstract: The present invention discloses an organic light emitting diode flexible array substrate including a displaying region, a folding region adjacent to the displaying region, a flexible substrate, barrier layer, a buffer layer, a polycrystalline layer stacked together, a first insulation layer disposed on the buffer layer and covering the polycrystalline layer, a first metal layer, a second metal layer, and a third metal layer. Folding signal lines are formed on a portion of the second metal layer in the folding region. Folding signal lines are formed on a portion of the third metal layer in the folding region. Double folding signal lines of the second metal layer and third metal layer drastically increase reliability and lifespan of the signal lines in the folding region.

Abstract: A flexible display device includes a display area, a first sector region, a first linear region, a second sector region, a second linear region, and a bonding region. A first signal line and a second signal line are disposed in the display area. A signal is transmitted through the first signal line and the second signal line disposed in a metal layer in the first sector region, the first linear region, the second sector region, the second linear region up to a metal layer in the bonding region. An overall resistance value of the first signal line is greater than an overall resistance value of the second signal line. Therefore, the problem of a difference in signal transmission speed and a difference in signal loss due to large resistant differences between different signal lines is effectively resolved.

Abstract: A pixel compensation circuit and an OLED display device are disclosed. Two or more TFTs are controlled by the scanning signal output from the scanning signal line in the same row in the pixel compensation circuit proposed by the present disclosure. Further, the OLED and the storage capacitor are both connected to the reset voltage signal line. So the OLED and the storage capacitor are reset after receiving the reset voltage signal. The size of the pixel structure in the horizontal direction is compressed in the pixel compensation circuit of the present disclosure, thereby providing space for the improvement of the PPI and facilitating the design of the high PPI panel successfully.

Abstract: An array substrate and an OLED display device are provided. A trace system of the array substrate is designed in a structure with three layers of metal. By providing one layer of inorganic insulation film and one layer of organic insulation film between two layers of metal, a coupling effect between two layers of trace can be reduced. By exposing all or part of an organic insulation film in a region, which will form a second electrode plate of a storage capacitor, a storage capacitor with larger capacitance can be formed. By forming a third metal layer as a mesh structure, it is possible to reduce IR drop without increasing mask and improve display uniformity of the display device.

Abstract: An array substrate and an OLED display device are provided. A trace system of the array substrate is designed in a structure with three layers of metal. By providing one layer of inorganic insulation film and one layer of organic insulation film between two layers of metal, a coupling effect between two layers of trace can be reduced. By exposing all or part of an organic insulation film in a region, which will form a second electrode plate of a storage capacitor, a storage capacitor with larger capacitance can be formed. By forming a third metal layer as a mesh structure, it is possible to reduce IR drop without increasing mask and improve display uniformity of the display device.

Abstract: A pixel compensation circuit and an OLED display device are disclosed. Two or more TFTs are controlled by the scanning signal output from the scanning signal line in the same row in the pixel compensation circuit proposed by the present disclosure. Further, the OLED and the storage capacitor are both connected to the reset voltage signal line. So the OLED and the storage capacitor are reset after receiving the reset voltage signal. The size of the pixel structure in the horizontal direction is compressed in the pixel compensation circuit of the present disclosure, thereby providing space for the improvement of the PPI and facilitating the design of the high PPI panel successfully.

Abstract: An electrostatic protection circuit of a display panel includes a first P-type thin film transistor having a gate connected to a high potential electrostatic output line and a drain connected to a high potential electrostatic output line, a second P-type thin film transistor having a gate connected to a high potential electrostatic output line and a drain connected to a source of the first P-type thin film transistor, and a source connected to the electrostatic signal input line; a first N-type thin film transistor having a gate connected to the low potential electrostatic output line, and a drain connected to the low potential electrostatic output line; a second N-type thin film transistor having a gate connected to the low potential electrostatic output line and a drain connected to the source of the first N-type thin film transistor, and a source connected to the electrostatic signal input line.

Abstract: An electrostatic protection circuit of a display panel includes a first P-type thin film transistor having a gate connected to a high potential electrostatic output line and a drain connected to a high potential electrostatic output line, a second P-type thin film transistor having a gate connected to a high potential electrostatic output line and a drain connected to a source of the first P-type thin film transistor, and a source connected to the electrostatic signal input line; a first N-type thin film transistor having a gate connected to the low potential electrostatic output line, and a drain connected to the low potential electrostatic output line; a second N-type thin film transistor having a gate connected to the low potential electrostatic output line and a drain connected to the source of the first N-type thin film transistor, and a source connected to the electrostatic signal input line.