Patents by Inventor Pinyen Lin
Pinyen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250022802Abstract: An integrated circuit (IC) with conductive structures and a method of fabricating the IC are disclosed. The method includes depositing a first dielectric layer on a semiconductor device, forming a conductive structure in the first dielectric layer, removing a portion of the first dielectric layer to expose a sidewall of the conductive structure, forming a barrier structure surrounding the sidewall of the conductive structure, depositing a conductive layer on the barrier structure, and performing a polishing process on the barrier structure and the conductive layer.Type: ApplicationFiled: July 13, 2023Publication date: January 16, 2025Applicant: Taiwan Semiconductor Manufacturing Co., LtdInventors: Tzu Pei Chen, Sung-Li Wang, Shin-Yi Yang, Po-Chin Chang, Yuting Cheng, Chia-Hung Chu, Chun-Hung Liao, Harry CHIEN, Chia-Hao Chang, Pinyen LIN
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Patent number: 12198939Abstract: A technique for semiconductor manufacturing is provided. The technique includes the operations as follows. A semiconductor structure having a first material is received. A plurality of first main etches are performed to the semiconductor structure for a plurality of first durations under the first etching chemistry. A plurality of pumping operations are performed for a plurality of pumping durations, each of the pumping operations being prior to each of the first main etches. Each of the first durations is in a range of from about 1 second to about 2.5 seconds.Type: GrantFiled: June 24, 2022Date of Patent: January 14, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Han-Yu Lin, Li-Te Lin, Tze-Chung Lin, Fang-Wei Lee, Yi-Lun Chen, Jung-Hao Chang, Yi-Chen Lo, Fo-Ju Lin, Kenichi Sano, Pinyen Lin
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Publication number: 20250014947Abstract: Methods of forming a metal gate structure of a stacked multi-gate device are provided. A method according to the present disclosure includes depositing a titanium nitride (TiN) layer over a channel region that includes bottom channel layers and top channel layers, depositing a dummy fill layer to cover sidewalls of the bottom channel layers, after the depositing of the dummy fill layer, selectively forming a blocking layer over the TiN layer along sidewalls of the top channel layers, selectively removing the dummy fill layer to release the bottom channel layers, selectively depositing a first work function metal layer to wrap around each of the bottom channel layers, forming a gate isolation layer over a top surface of the first work function metal layer, removing the blocking layer, releasing the top channel layers, and selectively depositing a second work function metal layer to wrap around each of the top channel layers.Type: ApplicationFiled: July 6, 2023Publication date: January 9, 2025Inventors: Kenichi Sano, Yi-Hsiu Chen, Pinyen Lin, Wei-Yen Woon
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Patent number: 12183805Abstract: A semiconductor device includes a substrate having a semiconductor fin. A gate structure is over the semiconductor fin, in which the gate structure has a tapered profile and comprises a gate dielectric. A work function metal layer is over the gate dielectric, and a filling metal is over the work function metal layer. A gate spacer is along a sidewall of the gate structure, in which the work function metal layer is in contact with the gate dielectric and a top portion of the gate spacer. An epitaxy structure is over the semiconductor fin.Type: GrantFiled: May 28, 2021Date of Patent: December 31, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Zhi-Qiang Wu, Kuo-An Liu, Chan-Lon Yang, Bharath Kumar Pulicherla, Li-Te Lin, Chung-Cheng Wu, Gwan-Sin Chang, Pinyen Lin
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Patent number: 12166037Abstract: A semiconductor device and methods of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure with first and second nanostructured layers on the fin structure, forming a polysilicon structure around the superlattice structure, forming a source/drain opening within the superlattice structure, forming a first conductivity type S/D region within a first portion of the S/D opening, forming an isolation layer on the first conductivity type S/D region and within a second portion of the S/D opening, forming a second conductivity type S/D region on the isolation layer and within a third portion the S/D opening, and replacing the polysilicon structure and the second nanostructured layers with a gate structure that surrounds the first nanostructured layers. Materials of the first and second nanostructured layers are different from each other and the second conductivity type is different from the first conductivity type.Type: GrantFiled: August 27, 2021Date of Patent: December 10, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Lun Chen, Pinyen Lin
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Publication number: 20240405093Abstract: The present disclosure describes forming a crystalline high-k dielectric layer at a reduced crystallization temperature in a semiconductor device. The method includes forming a channel structure on a substrate, forming an interfacial layer on the channel structure, forming a first high-k dielectric layer on the interfacial layer, forming dipoles in the first high-k dielectric layer with a dopant, and forming a second high-k dielectric layer on the first high-k dielectric layer. The dopant includes a first metal element. The second high-k dielectric layer includes a second metal element different from the first metal element.Type: ApplicationFiled: June 2, 2023Publication date: December 5, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shen-Yang LEE, Hsiang-Pi CHANG, Huang-Lin CHAO, Pinyen LIN
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Publication number: 20240395626Abstract: A method for fabricating a semiconductor arrangement includes performing a first etching of a semiconductive structure to expose a first portion of a sidewall of a first layer adjacent the semiconductive structure. The first etching forms a first protective layer on the first portion of the sidewall of the first layer, and the first protective layer is formed from a first accumulation of by-product material formed from an etchant of the first etching interacting with the semiconductive structure. The method includes performing a first flash to remove at least some of the first protective layer.Type: ApplicationFiled: July 31, 2024Publication date: November 28, 2024Inventors: Wei-Lun CHEN, Chao-Hsien HUANG, Li-Te LIN, Pinyen LIN
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Publication number: 20240395855Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, first and second fin structures formed over the substrate, and an isolation structure between the first and second fin structures. The isolation structure can include a lower portion and an upper portion. The lower portion of the isolation structure can include a metal-free dielectric material. The upper portion of the isolation structure can include a metallic element and silicon.Type: ApplicationFiled: July 30, 2024Publication date: November 28, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pinyen LIN, Chin-Hsiang LIN, Huang-Lin CHAO
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Patent number: 12154970Abstract: A method for forming a semiconductor device structure is provided. The method includes forming first semiconductor layers and second semiconductor layers on a substrate, and the first semiconductor layers and the second semiconductor layers are alternately stacked. The method includes forming a dummy gate structure over the first semiconductor layers and the second semiconductor layers, and removing a portion of the first semiconductor layers and second semiconductor layers to form a S/D trench. The method also includes removing the second semiconductor layers to form a recess connected to the S/D trench. The method includes forming a dummy dielectric layer in the recess after the dummy gate structure is formed, and the dummy dielectric layer is exposed by the S/D trench. The method includes removing a portion of the dummy dielectric layer to form a cavity and forming an inner spacer layer in the cavity.Type: GrantFiled: June 30, 2022Date of Patent: November 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tze-Chung Lin, Han-Yu Lin, Li-Te Lin, Pinyen Lin
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Patent number: 12154969Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a metal gate stack over the substrate. The metal gate stack has a gate dielectric layer and a work function layer over the gate dielectric layer. The semiconductor device structure also includes a spacer structure over a sidewall of the metal gate stack. A topmost surface of the gate dielectric layer is lower than a topmost surface of the spacer structure. The topmost surface of the gate dielectric layer is closer to the topmost surface of the spacer structure than a topmost surface of the work function layer.Type: GrantFiled: November 22, 2021Date of Patent: November 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Hao Chang, Li-Te Lin, Pinyen Lin
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Publication number: 20240387693Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include first and second sacrificial layers. The method can further include forming a recess structure in a first portion of the fin structure, selectively etching the first sacrificial layer of a second portion of the fin structure over the second sacrificial layer of the second portion of the fin structure, and forming an inner spacer layer over the etched first sacrificial layer with the second sacrificial layer of the second portion of the fin structure being exposed.Type: ApplicationFiled: July 29, 2024Publication date: November 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Hao Chang, Fo-Ju Lin, Fang-Wei Lee, Li-Te Lin, Pinyen Lin
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Publication number: 20240379793Abstract: A method for fabricating a semiconductor device includes exposing one or more surfaces of a conduction channel of a transistor; overlaying the one or more surfaces with a dielectric interfacial layer; overlaying the dielectric interfacial layer with a blocking layer; performing a first annealing process to densify the dielectric interfacial layer, overlaying the blocking layer with a first high-k dielectric layer; forming one or more threshold voltage modulation layers over the first high-k dielectric layer; performing a second annealing process to adjust a doping profile of the first high-k dielectric layer; and overlaying the first high-k dielectric layer with a second high-k dielectric layer.Type: ApplicationFiled: May 8, 2023Publication date: November 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shen-Yang Lee, Hsiang-Pi Chang, Huang-Lin Chao, Pinyen Lin
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Publication number: 20240381667Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.Type: ApplicationFiled: July 23, 2024Publication date: November 14, 2024Inventors: Kuan-Liang Liu, Sheng-Chau Chen, Chung-Liang Cheng, Chia-Shiung Tsai, Yeong-Jyh Lin, Pinyen Lin, Huang-Lin Chao
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Publication number: 20240379333Abstract: The present disclosure relates to a semiconductor device manufacturing system. The semiconductor device manufacturing system can include a chamber and an ion source in the chamber. The ion source can include an outlet. The ion source can be configured to generate a particle beam. The semiconductor device manufacturing system can further include a grid structure proximate to the outlet of the ion source and configured to manipulate the particle beam. A first portion of the grid structure can be electrically insulated from a second portion of the grid structure.Type: ApplicationFiled: July 23, 2024Publication date: November 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, LTD.Inventors: Jung-Hao Chang, Po-Chin CHANG, Pinyen LIN, Li-Te LIN
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Publication number: 20240363421Abstract: The present disclosure describes a semiconductor device with a rare earth metal oxide layer and a method for forming the same. The method includes forming fin structures on a substrate and forming superlattice structures on the fin structures, where each of the superlattice structures includes a first-type nanostructured layer and a second-type nanostructured layer. The method further includes forming an isolation layer between the superlattice structures, implanting a rare earth metal into a top portion of the isolation layer to form a rare earth metal oxide layer, and forming a polysilicon structure over the superlattice structures. The method further includes etching portions of the superlattice structures adjacent to the polysilicon structure to form a source/drain (S/D) opening and forming an S/D region in the S/D opening.Type: ApplicationFiled: July 8, 2024Publication date: October 31, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Yu LIN, Szu-Hua Chen, Kuan-Kan Hu, Kenichi Sano, Po-Cheng Wang, Wei-Yen Woon, Pinyen Lin, Che Chi Shih
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Publication number: 20240363721Abstract: A semiconductor device and methods of fabricating the same are disclosed. The method can include forming a fin structure on a substrate, forming a source/drain (S/D) region on the fin structure, forming a gate structure on the fin structure adjacent to the S/D region, and forming a capping structure on the gate structure. The forming the capping structure includes forming a conductive cap on the gate structure, forming a cap liner on the conductive cap, and forming a carbon-based cap on the cap liner. The method further includes forming a first contact structure on the S/D region, forming an insulating cap on the first contact structure, and forming a second contact structure on the conductive cap.Type: ApplicationFiled: July 12, 2024Publication date: October 31, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Chin CHANG, Ming-Huan TSAI, Li-Te LIN, Pinyen LIN
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Publication number: 20240363632Abstract: A semiconductor device and methods of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure with first and second nanostructured layers on the fin structure, forming a polysilicon structure around the superlattice structure, forming a source/drain opening within the superlattice structure, forming a first conductivity type S/D region within a first portion of the S/D opening, forming an isolation layer on the first conductivity type S/D region and within a second portion of the S/D opening, forming a second conductivity type S/D region on the isolation layer and within a third portion the S/D opening, and replacing the polysilicon structure and the second nanostructured layers with a gate structure that surrounds the first nanostructured layers. Materials of the first and second nanostructured layers are different from each other and the second conductivity type is different from the first conductivity type.Type: ApplicationFiled: July 12, 2024Publication date: October 31, 2024Applicant: Taiwan Semiconductor Manufacuring Copany, Ltd.Inventors: Wei-Lun CHEN, Pinyen LIN
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Publication number: 20240347345Abstract: A semiconductor fabrication apparatus includes a processing chamber for etching, a substrate stage integrated in the processing chamber and being configured to secure a semiconductor wafer, and a gas distribution plate integrated inside the processing chamber. The processing chamber includes a sidewall and a top surface. The semiconductor fabrication apparatus further includes a heating mechanism disposed on the sidewall of the processing chamber and is operable to perform a baking process to remove a by-product generated during the etching, and a reflective mirror configured inside the processing chamber to reflect thermal energy from the heating mechanism toward the semiconductor wafer, the reflective mirror being located on the top surface of the processing chamber. The gas distribution plate defines a portion of the top surface of the processing chamber. From a top view, a portion of the reflective mirror is disposed between the heating mechanism and the gas distribution plate.Type: ApplicationFiled: June 24, 2024Publication date: October 17, 2024Inventors: Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Li-Te Lin, Pinyen Lin, Tze-Chung Lin
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Publication number: 20240332393Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.Type: ApplicationFiled: June 13, 2024Publication date: October 3, 2024Applicant: Taiwan Semiconductor Manufacturing Company, LTD.Inventors: Hsu-Kai CHANG, Jhih-Rong HUANG, Yen-Tien TUNG, Chia-Hung CHU, Shuen-Shin LIANG, Tzer-Min SHEN, Pinyen LIN, Sung-Li WANG
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Publication number: 20240322003Abstract: A method for manufacturing a semiconductor device includes: forming a semiconductor stack on a semiconductor substrate in a flat state, the semiconductor stack including sacrificial layer portions and channel layer portions that are alternately stacked over one another; forming source/drain trenches in the semiconductor stack, each of the source/drain trenches penetrating the channel layer portions, the sacrificial layer portions and an upper portion of the semiconductor substrate, and terminating at a lower portion of the semiconductor substrate, so as to form the channel layer portions into channel features and form the sacrificial layer portions into sacrificial features; transforming the semiconductor substrate from the flat state to a bending state; forming source/drain regions in the source/drain trenches, respectively; and reverting the semiconductor substrate from the bending state back to the flat state, so as to induce a strain in the channel features.Type: ApplicationFiled: March 20, 2023Publication date: September 26, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Ling PAI, Hsiang-Pi CHANG, Shen-Yang LEE, Fu-Ting YEN, Huang-Lin CHAO, Pinyen LIN, I-Ming CHANG