Patents by Inventor Pinyen Lin
Pinyen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250261436Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.Type: ApplicationFiled: April 2, 2025Publication date: August 14, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Yu LIN, Jhih-Rong HUANG, Yen-Tien TUNG, Tzer-Min SHEN, Fu-Ting YEN, Gary CHAN, Keng-Chu LIN, Li-Te LIN, Pinyen LIN
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Patent number: 12376337Abstract: The present disclosure describes a method to form a semiconductor device with air inner spacers. The method includes forming a semiconductor structure on a first side of a substrate. The semiconductor structure includes a fin structure having multiple semiconductor layers on the substrate, an epitaxial structure on the substrate and in contact with the multiple semiconductor layers, a gate structure wrapped around the multiple semiconductor layers, and an inner spacer structure between the gate structure and the epitaxial structure. The method further includes removing a portion of the substrate from a second side of the substrate to expose the epitaxial structure and the inner spacer structure, forming an oxide layer on the epitaxial structure on the second side of the substrate, and removing a portion of the inner spacer structure to form an opening. The second side is opposite to the first side of the substrate.Type: GrantFiled: September 10, 2021Date of Patent: July 29, 2025Inventors: Fo-Ju Lin, Fang-Wei Lee, Chih-Long Chiang, Li-Te Lin, Pinyen Lin
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Patent number: 12363962Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, first and second fin structures formed over the substrate, and an isolation structure between the first and second fin structures. The isolation structure can include a lower portion and an upper portion. The lower portion of the isolation structure can include a metal-free dielectric material. The upper portion of the isolation structure can include a metallic element and silicon.Type: GrantFiled: August 27, 2021Date of Patent: July 15, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pinyen Lin, Chin-Hsiang Lin, Huang-Lin Chao
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Patent number: 12341056Abstract: A method of fabricating a semiconductor structure and the semiconductor structure are disclosed. The method uses high flow rate of an etchant and an optimized scan pattern, so that the obtained semiconductor structure is a device upside-down bonded to the carrier wafer without any silicon remaining and is ready for subsequent lithography process for back via contact.Type: GrantFiled: August 30, 2021Date of Patent: June 24, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Kenichi Sano, Chung-Liang Cheng, De-Yang Chiou, Kuanliang Liu, Pinyen Lin
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Patent number: 12336252Abstract: A method for forming a semiconductor structure includes forming a fin on a semiconductor substrate. The fin includes channel layers and sacrificial layers stacked one on top of the other in an alternating fashion. The method also includes removing a portion of the fin to form a first opening and expose vertical sidewalls of the channel layers and the sacrificial layers, epitaxially growing a source/drain feature in the first opening from the exposed vertical sidewalls of the channel layers and the sacrificial layers, removing another portion of the fin to form a second opening to expose a vertical sidewall of the source/drain feature, depositing a dielectric layer in the second opening to cover the exposed vertical sidewall of the source/drain feature, and replacing the sacrificial layers with a metal gate structure in the second opening. The dielectric layer separates the source/drain feature from contacting the metal gate structure.Type: GrantFiled: December 15, 2022Date of Patent: June 17, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Han-Yu Lin, Chansyun David Yang, Tze-Chung Lin, Fang-Wei Lee, Fo-Ju Lin, Li-Te Lin, Pinyen Lin
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Patent number: 12327788Abstract: A method for manufacturing a semiconductor device includes: forming a lower metal contact in a trench of a first dielectric structure, the lower metal contact having a height less than a depth of the trench and being made of a first metal material; forming an upper metal contact to fill the trench and to be in contact with the lower metal contact, the upper metal contact being formed of a second metal material different from the first metal material and having a bottom surface with a dimension the same as a dimension of a top surface of the lower metal contact; forming a second dielectric structure on the first dielectric structure; and forming a via contact penetrating through the second dielectric structure to be electrically connected to the upper metal contact, the via contact being formed of a metal material the same as the second metal material.Type: GrantFiled: January 18, 2022Date of Patent: June 10, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shuen-Shin Liang, Chia-Hung Chu, Po-Chin Chang, Tzu-Pei Chen, Ken-Yu Chang, Hung-Yi Huang, Harry Chien, Wei-Yip Loh, Chun-I Tsai, Hong-Mao Lee, Sung-Li Wang, Pinyen Lin
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Publication number: 20250185346Abstract: A method includes forming a semiconductor fin protruding from a substrate and depositing a dielectric layer over the substrate. The dielectric layer has a first portion deposited on a first sidewall of the semiconductor fin and a second portion deposited on the second sidewall of the semiconductor fin. The method further includes implanting impurities into the first and second portions of the dielectric layer. The impurities reach a first depth in the first portion of the dielectric layer and a second depth in the second portion of the dielectric layer. The first depth is smaller than the second depth. The method further includes recessing the dielectric layer to expose the first and second sidewalls of the semiconductor fin.Type: ApplicationFiled: February 5, 2025Publication date: June 5, 2025Inventors: Han-Yu Lin, Akira Mineji, Chao-Hsien Huang, Pinyen Lin, Yi-Ruei Jhan, Fang-Wei Lee, Tze-Chung Lin, Li-Te Lin
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Publication number: 20250149343Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.Type: ApplicationFiled: January 10, 2025Publication date: May 8, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ya-Wen YEH, Yu-Tien SHEN, Shih-Chun HUANG, Po-Chin CHANG, Wei-Liang LIN, Yung-Sung YEN, Wei-Hao WU, Li-Te LIN, Pinyen LIN, Ru-Gun LIU
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Patent number: 12288722Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.Type: GrantFiled: January 2, 2023Date of Patent: April 29, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Yu Lin, Jhih-Rong Huang, Yen-Tien Tung, Tzer-Min Shen, Fu-Ting Yen, Gary Chan, Keng-Chu Lin, Li-Te Lin, Pinyen Lin
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Publication number: 20250118666Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a substrate and at least one contact plug. The substrate has an epi-layer. The contact plug is formed on the epi-layer and includes a silicide cap disposed on the epi-layer; a conductive pillar disposed on the silicide cap such that the conductive pillar electrically connects to the epi-layer via the silicide cap; and a hybrid liner. The hybrid liner surrounds the conductive pillar and includes a lower portion abutting the silicide cap and having a nitride material and an upper portion abutting the conductive pillar and having an oxidized nitride material. Due to the hybrid liner, a semiconductor structure with increased capacitance and decreased resistivity can be obtained.Type: ApplicationFiled: October 10, 2023Publication date: April 10, 2025Inventors: TZU PEI CHEN, MIN-HSUAN LU, HAO-HENG LIU, YUTING CHENG, HSU-KAI CHANG, PO-CHIN CHANG, OLIVIA PEI-HUA LEE, SHENG-TSUNG WANG, HUAN-CHIEH SU, SUNG-LI WANG, PINYEN LIN
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Patent number: 12272752Abstract: A semiconductor device structure is provided. The semiconductor device structure includes multiple semiconductor nanostructures, and the semiconductor nanostructures include a first semiconductor material. The semiconductor device structure also includes multiple epitaxial structures extending from edges of the semiconductor nanostructures. The epitaxial structures include a second semiconductor material that is different than the first semiconductor material. The semiconductor device structure further includes a gate stack wrapped around the semiconductor nanostructures.Type: GrantFiled: November 29, 2023Date of Patent: April 8, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shuen-Shin Liang, Pang-Yen Tsai, Keng-Chu Lin, Sung-Li Wang, Pinyen Lin
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Publication number: 20250113517Abstract: A method of forming source/drain regions of semiconductor devices is disclosed. The method includes forming a fin structure on a substrate, forming a polysilicon structure on the fin structure, removing a portion of the fin structure adjacent to the polysilicon structure to form an opening, and forming a S/D region in the opening. The forming the S/D region includes exposing the fin structure in the opening to a first flow rate of a precursor gas during a first phase of a gas flow cycle, a second flow rate of the precursor gas during a second phase of the gas flow cycle. The exposing the fin structure in the opening to the precursor gas, the etching gas, and the plasma is performed in an in-situ process.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shao-An WANG, Ding-Kang SHIH, Chia-Ling PAI, Pinyen LIN
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Publication number: 20250113604Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method includes forming first channel structures, second channel structures, and third channel structures. The method also includes forming gate dielectric layers surrounding the first channel structures, the second channel structures, and the third channel structures and forming dipole layers over the gate dielectric layers. The method also includes forming a dummy material in a first space between the first and the second channel structures and in a second space between the second and the third channel structures and removing first portions of the dummy material. The method also includes implanting first dopants in the dummy material in the first space and removing second portions of the dummy material in the first space and the second space. The method also includes removing the dipole layers in the top device region and completely removing the dummy material.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kenichi SANO, Chia-Yun CHENG, Yu-Wei LU, I-Ming CHANG, Pinyen LIN
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Publication number: 20250105019Abstract: A method is provided. The method includes: receiving a semiconductor structure having a first material and a second material; performing a first etch on the first material for a first duration under a first etching chemistry; and performing a second etch on the second material for a second duration under a second etching chemistry, wherein the first material includes a first incubation time and the second material includes a second incubation time greater than the first incubation time under the first etching chemistry. The first material includes a third incubation time and the second material includes a fourth incubation time less than the third incubation time under the second etching chemistry.Type: ApplicationFiled: December 10, 2024Publication date: March 27, 2025Inventors: HAN-YU LIN, LI-TE LIN, TZE-CHUNG LIN, FANG-WEI LEE, YI-LUN CHEN, JUNG-HAO CHANG, YI-CHEN LO, FO-JU LIN, KENICHI SANO, PINYEN LIN
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Publication number: 20250089332Abstract: A semiconductor device includes a substrate having a semiconductor fin. A gate structure is over the semiconductor fin, in which the gate structure has a tapered profile and comprises a gate dielectric. A work function metal layer is over the gate dielectric, and a filling metal is over the work function metal layer. A gate spacer is along a sidewall of the gate structure, in which the work function metal layer is in contact with the gate dielectric and a top portion of the gate spacer. An epitaxy structure is over the semiconductor fin.Type: ApplicationFiled: November 27, 2024Publication date: March 13, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Zhi-Qiang WU, Kuo-An LIU, Chan-Lon YANG, Bharath Kumar PULICHERLA, Li-Te LIN, Chung-Cheng WU, Gwan-Sin CHANG, Pinyen LIN
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Publication number: 20250089331Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a stack structure over a substrate, and the stack structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked. The method includes forming a dummy gate electrode over the first semiconductor layers and the second semiconductor layers, and forming a gate spacer layer adjacent to the dummy gate electrode. The method includes removing the second semiconductor layers to form a recess between two adjacent first semiconductor layers, and forming a dummy dielectric layer in the recess after the dummy gate electrode is formed. The dummy dielectric layer is between two adjacent first semiconductor layers. The method includes replacing the dummy gate electrode and the dummy dielectric layer with a gate structure.Type: ApplicationFiled: November 25, 2024Publication date: March 13, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tze-Chung LIN, Han-Yu LIN, Li-Te LIN, Pinyen LIN
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Patent number: 12230507Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.Type: GrantFiled: April 25, 2023Date of Patent: February 18, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ya-Wen Yeh, Yu-Tien Shen, Shih-Chun Huang, Po-Chin Chang, Wei-Liang Lin, Yung-Sung Yen, Wei-Hao Wu, Li-Te Lin, Pinyen Lin, Ru-Gun Liu
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Publication number: 20250056860Abstract: A semiconductor device structure includes a substrate and a metal gate stack over the substrate. The metal gate stack has a gate dielectric layer and a work function layer over the gate dielectric layer, and the gate dielectric layer has a curved sidewall and a vertical sidewall. The semiconductor device structure also includes a protection element over the metal gate stack, and the protection element extends conformally along the curved sidewall and the vertical sidewall to reach a topmost surface of the work function layer. The semiconductor device structure further includes a spacer structure over a sidewall of the metal gate stack. A topmost surface of the gate dielectric layer is lower than a topmost surface of the spacer structure, and the topmost surface of the gate dielectric layer is closer to the topmost surface of the spacer structure than the topmost surface of the work function layer.Type: ApplicationFiled: October 28, 2024Publication date: February 13, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Hao CHANG, Li-Te LIN, Pinyen LIN
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Patent number: 12224210Abstract: A semiconductor device includes a substrate, a semiconductor fin protruding from the substrate, an isolation layer disposed above the substrate, a dielectric fin with a bottom portion embedded in the isolation layer, and a gate structure over top and sidewall surfaces of the semiconductor fin and the dielectric fin. The semiconductor fin has a first sidewall and a second sidewall facing away from the first sidewall. The isolation layer includes a first portion disposed on the first sidewall of the semiconductor fin and a second portion disposed on the second sidewall of the semiconductor fin. A top portion of the dielectric fin includes an air pocket with a top opening sealed by the gate structure.Type: GrantFiled: May 8, 2023Date of Patent: February 11, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Tze-Chung Lin, Chao-Hsien Huang, Li-Te Lin, Pinyen Lin, Akira Mineji
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Patent number: 12218219Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include first and second sacrificial layers. The method can further include forming a recess structure in a first portion of the fin structure, selectively etching the first sacrificial layer of a second portion of the fin structure over the second sacrificial layer of the second portion of the fin structure, and forming an inner spacer layer over the etched first sacrificial layer with the second sacrificial layer of the second portion of the fin structure being exposed.Type: GrantFiled: August 27, 2021Date of Patent: February 4, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jung-Hao Chang, Fo-Ju Lin, Fang-Wei Lee, Li-Te Lin, Pinyen Lin