Patents by Inventor Pinyen Lin

Pinyen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210257478
    Abstract: A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.
    Type: Application
    Filed: May 3, 2021
    Publication date: August 19, 2021
    Inventors: Po-Chin Chang, Wei-Hao Wu, Li-Te Lin, Pinyen Lin
  • Patent number: 11094556
    Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: August 17, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ya-Wen Yeh, Yu-Tien Shen, Shih-Chun Huang, Po-Chin Chang, Wei-Liang Lin, Yung-Sung Yen, Wei-Hao Wu, Li-Te Lin, Pinyen Lin, Ru-Gun Liu
  • Publication number: 20210210614
    Abstract: A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.
    Type: Application
    Filed: March 19, 2021
    Publication date: July 8, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen LO, Jung-Hao CHANG, Li-Te LIN, Pinyen LIN
  • Patent number: 11056393
    Abstract: A method for FinFET fabrication includes forming at least three semiconductor fins over a substrate, wherein first, second, and third of the semiconductor fins are lengthwise substantially parallel to each other, spacing between the first and second semiconductor fins is smaller than spacing between the second and third semiconductor fins; depositing a first dielectric layer over top and sidewalls of the semiconductor fins, resulting in a trench between the second and third semiconductor fins, bottom and two opposing sidewalls of the trench being the first dielectric layer; implanting ions into one of the two opposing sidewalls of the trench by a first tilted ion implantation process; implanting ions into another one of the two opposing sidewalls of the trench by a second tilted ion implantation process; depositing a second dielectric layer into the trench, the first and second dielectric layers having different materials; and etching the first dielectric layer.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: July 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Tze-Chung Lin, Chao-Hsien Huang, Li-Te Lin, Pinyen Lin, Akira Mineji
  • Publication number: 20210202247
    Abstract: A method includes forming a gate spacer on sidewalls of a dummy gate structure disposed over a semiconductor substrate; performing a first implantation process to the gate spacer, wherein the first implantation process includes bombarding an upper portion of the gate spacer with silicon atoms; after performing the first implantation process, performing a second implantation process to the upper portion of the gate spacer, where the second implantation process includes bombarding the upper portion of the gate spacer with carbon atoms; and after performing the second implantation process, replacing the dummy gate structure with a high-k metal gate structure, wherein the replacing includes forming an interlayer dielectric (ILD) layer.
    Type: Application
    Filed: March 15, 2021
    Publication date: July 1, 2021
    Inventors: Yi-Ruei Jhan, Han-Yu Lin, Li-Te Lin, Pinyen Lin
  • Patent number: 11043381
    Abstract: A directional patterning method includes following steps. A substrate is provided with a mask layer thereon, and the mask layer has at least one opening pattern therein. A cyclic deposition and etching process is performed to increase a length of the at least one opening pattern.
    Type: Grant
    Filed: January 27, 2019
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chin Chang, Li-Te Lin, Ru-Gun Liu, Wei-Liang Lin, Pinyen Lin, Yu-Tien Shen, Ya-Wen Yeh
  • Patent number: 11024721
    Abstract: A method includes forming a dummy gate over a substrate. A pair of gate spacers are formed on opposite sidewalls of the dummy gate. The dummy gate is removed to form a trench between the gate spacers. A first ion beam is directed to an upper portion of the trench, while leaving a lower portion of the trench substantially free from incidence of the first ion beam. The substrate is moved relative to the first ion beam during directing the first ion beam to the trench. A gate structure is formed in the trench.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: June 1, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Qiang Wu, Kuo-An Liu, Chan-Lon Yang, Bharath Kumar Pulicherla, Li-Te Lin, Chung-Cheng Wu, Gwan-Sin Chang, Pinyen Lin
  • Patent number: 10998421
    Abstract: A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chin Chang, Wei-Hao Wu, Li-Te Lin, Pinyen Lin
  • Patent number: 10957779
    Abstract: A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen Lo, Jung-Hao Chang, Li-Te Lin, Pinyen Lin
  • Patent number: 10950434
    Abstract: A method includes forming a gate spacer on sidewalls of a dummy gate structure disposed over a semiconductor substrate; performing a first implantation process to the gate spacer, wherein the first implantation process includes bombarding an upper portion of the gate spacer with silicon atoms; after performing the first implantation process, performing a second implantation process to the upper portion of the gate spacer, wherein the second implantation process includes bombarding the upper portion of the gate spacer with carbon atoms; and after performing the second implantation process, replacing the dummy gate structure with a high-k metal gate structure, wherein the replacing includes forming an interlayer dielectric (ILD) layer.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: March 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Ruei Jhan, Han-Yu Lin, Li-Te Lin, Pinyen Lin
  • Publication number: 20210066490
    Abstract: The current disclosure describes techniques for forming a gate-all-around device where semiconductor layers are released by etching out the buffer layers that are vertically stacked between semiconductor layers in an alternating manner. The buffer layers stacked at different vertical levels include different material compositions, which bring about different etch rates with respect to an etchant that is used to remove at least partially the buffer layers to release the semiconductor layers.
    Type: Application
    Filed: September 3, 2019
    Publication date: March 4, 2021
    Inventors: Chansyun David Yang, Han-Yu Lin, Chun-Yu Chen, Chih-Ching Wang, Fang-Wei Lee, Tze-Chung LIN, Li-Te LIN, Gwan-Sin Chang, Pinyen LIN
  • Publication number: 20210013103
    Abstract: A semiconductor device includes a semiconductor substrate, a source/drain region, a source/drain contact, a conductive via and a first polymer layer. The source/drain region is in the semiconductor substrate. The source/drain contact is over the source/drain region. The source/drain via is over the source/drain contact. The first polymer layer extends along a first sidewall of the conductive via and is separated from a second sidewall of the conductive via substantially perpendicular to the first sidewall of the conductive via.
    Type: Application
    Filed: September 25, 2020
    Publication date: January 14, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Chin CHANG, Li-Te LIN, Pinyen LIN
  • Publication number: 20200411378
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack and a source/drain contact structure formed over a substrate. A first gate spacer is separated the gate stack from the source/drain contact structure and extends above top surfaces of the gate stack and the source/drain contact structure. An insulating capping layer covers the top surface of the gate stack and extends on the top surface of the first gate spacer. A conductive via structure partially covers the top surface of the insulating capping layer and the top surface of the source/drain contact structure. A first insulating layer surrounds the conductive via structure and partially covers the top surface of the source/drain contact structure.
    Type: Application
    Filed: September 11, 2020
    Publication date: December 31, 2020
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Jui HUANG, Li-Te LIN, Pinyen LIN
  • Publication number: 20200381535
    Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a dummy gate stack over a semiconductor substrate and forming spacer elements over sidewalls of the dummy gate stack. The method also includes removing the dummy gate stack to form a recess between the spacer elements and forming a metal gate stack in the recess. The method further includes etching back the metal gate stack while the metal gate stack is kept at a temperature that is in a range from about 20 degrees C. to about 55 degrees C. In addition, the method includes forming a protection element over the metal gate stack after etching back the metal gate stack.
    Type: Application
    Filed: November 6, 2019
    Publication date: December 3, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jung-Hao Chang, Li-Te Lin, Pinyen Lin
  • Patent number: 10847633
    Abstract: In some embodiments, a method is provided. Dummy gate stacks are formed over a semiconductor substrate. An interlayer dielectric (ILD) layer is formed over the dummy gate stacks. A first portion of the ILD layer over top surfaces of the dummy gate stacks is removed, such that a second portion of the ILD layer remains between the dummy gate stacks. The dummy gate stacks are replaced with metal gate stacks. Neutral NF3 radicals into the water are applied to etch the ILD layer.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Ruei Jhan, Yi-Lun Chen, Fang-Wei Lee, Han-Yu Lin, Li-Te Lin, Pinyen Lin
  • Publication number: 20200357899
    Abstract: A semiconductor device includes a substrate, a semiconductor fin, a gate electrode, a pair of gate spacers, a dielectric cap, and a hard mask layer. The semiconductor fin extends upwardly from the substrate. The gate electrode straddles the semiconductor fin. The pair of gate spacers is on opposite sidewalls of the gate electrode. The dielectric cap is atop the gate electrode and laterally between the pair of gate spacers. The hard mask layer is atop the dielectric cap and laterally between the pair of gate spacers. A bottommost position of the hard mask layer is not lower than a topmost position of the dielectric cap.
    Type: Application
    Filed: July 24, 2020
    Publication date: November 12, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen LO, Li-Te LIN, Pinyen LIN
  • Publication number: 20200335340
    Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.
    Type: Application
    Filed: July 6, 2020
    Publication date: October 22, 2020
    Inventors: Shih-Chun HUANG, Chiu-Hsiang CHEN, Ya-Wen YEH, Yu-Tien SHEN, Po-Chin CHANG, Chien Wen LAI, Wei-Liang LIN, Ya Hui CHANG, Yung-Sung YEN, Li-Te LIN, Pinyen LIN, Ru-Gun LIU, Chin-Hsiang LIN
  • Patent number: 10790195
    Abstract: A method includes following steps. A semiconductor fin is formed on a substrate and extends in a first direction. A source/drain region is formed on the semiconductor fin and a first interlayer dielectric (ILD) layer over the source/drain region. A gate stack is formed across the semiconductor fin and extends in a second direction substantially perpendicular to the first direction. A patterned mask having a first opening is formed over the first ILD layer. A protective layer is formed in the first opening using a deposition process having a faster deposition rate in the first direction than in the second direction. After forming the protective layer, the first opening is elongated in the second direction. A second opening is formed in the first ILD layer and under the elongated first opening. A conductive material is formed in the second opening.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: September 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Chin Chang, Li-Te Lin, Pinyen Lin
  • Publication number: 20200294851
    Abstract: A semiconductor structure includes a semiconductor substrate, a gate structure, an etch stop layer, a dielectric structure, and a conductive material. The gate structure is on the semiconductor substrate. The etch stop layer is over the gate structure. The dielectric structure is over the etch stop layer, in which the dielectric structure has a ratio of silicon to nitrogen varying from a middle layer of the dielectric structure to a bottom layer of the dielectric structure. The conductive material extends through the dielectric structure.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 17, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Chang SUN, Po-Chin CHANG, Akira MINEJI, Zi-Wei FANG, Pinyen LIN
  • Patent number: 10777455
    Abstract: A method for forming a semiconductor device structure is provided. A gate structure and a source/drain contact structure are formed over a substrate. The gate structure is covered with a capping layer. The capping layer and the source/drain contact structure are successively covered with a first insulating layer and a second insulating layer. A via opening is formed in the second insulating layer to expose the first insulating layer above the source/drain contact structure. The exposed first insulating layer is recessed using a first etching gas mixture including an oxygen gas, to leave a portion of the first insulating layer. The left portion of the first insulating layer using a second etching gas mixture including a hydrogen gas, to expose the source/drain contact structure. A conductive material is formed in the via opening to electrically connect the source/drain contact structure.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: September 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Jui Huang, Li-Te Lin, Pinyen Lin