Patents by Inventor Piotr Edelman

Piotr Edelman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180315630
    Abstract: A method for measuring charging of a semiconductor wafer associated with processing the semiconductor wafer includes using a probe assembly at a charge monitoring module to measure a charge on the semiconductor wafer prior to processing the semiconductor wafer using a processing tool, the probe assembly being located proximate to a processing station of the processing tool; transferring the semiconductor wafer from the charge monitoring module to the processing station using an automated wafer handling apparatus; processing the semiconductor wafer at the processing station using the processing tool; transferring the processed wafer from the processing station back to the charge monitoring module; using the probe assembly at the charge monitoring module to measure a charge on the semiconductor wafer after processing the wafer; and analyzing the measured charge on the semiconductor wafer both before and after processing the semiconductor wafer to determine information about charging of the wafer due to processi
    Type: Application
    Filed: May 1, 2018
    Publication date: November 1, 2018
    Inventors: Dmitriy Marinskiy, Andrew Findlay, Bret Schrayer, Jacek Lagowski, Piotr Edelman, Alexandre Savtchouk
  • Patent number: 7202691
    Abstract: A non-contact method is described for acquiring the accurate charge-voltage data on miniature test sites of semiconductor wafer wherein the test sites are smaller than 100 ?m times 100 ?m. The method includes recognizing the designated test site, properly aligning it, depositing a prescribed dose of ionic charge on the surface of the test site, and precise measuring of the resulting voltage change on the surface of the test site. The method further compromises measuring of the said voltage change in the dark and/or under strong illumination without interference from the laser beam employed in the Kelvin Force probe measurement of the voltage. The method enables acquiring of charge-voltage data without contacting the measured surface of the wafer and without contaminating the wafer. Thus, the measured wafer can be returned to IC fabrication line for further processing.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: April 10, 2007
    Assignee: Semiconductor Diagnostics, Inc.
    Inventors: Jacek Lagowski, Piotr Edelman, Dmitriy Marinskiy, Joseph Nicholas Kochey, Carlos Almeida
  • Publication number: 20060267622
    Abstract: A non-contact method is described for acquiring the accurate charge-voltage data on miniature test sites of semiconductor wafer wherein the test sites are smaller than 100 ?m times 100 ?m. The method includes recognizing the designated test site, properly aligning it, depositing a prescribed dose of ionic charge on the surface of the test site, and precise measuring of the resulting voltage change on the surface of the test site. The method further compromises measuring of the said voltage change in the dark and/or under strong illumination without interference from the laser beam employed in the Kelvin Force probe measurement of the voltage. The method enables acquiring of charge-voltage data without contacting the measured surface of the wafer and without contaminating the wafer. Thus, the measured wafer can be returned to IC fabrication line for further processing.
    Type: Application
    Filed: July 27, 2005
    Publication date: November 30, 2006
    Inventors: Jacek Lagowski, Piotr Edelman, Dmitriy Marinskiy, Joseph Kochey, Carlos Almeida
  • Patent number: 6771091
    Abstract: Techniques for measuring a contact potential difference of a sample at an elevated temperature using a probe designed for room temperature measurement are disclosed. In such measurements, probe damage by excessive heating can be prevented without any probe modifications to include probe cooling. This can be achieved by minimizing the time the probe spends in close proximity to the heated sample. Furthermore, the effect of probe heating by the sample on the probe reading can be corrected by including an additional contact potential difference measurement of a reference plate kept at room temperature in the measurement cycle.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: August 3, 2004
    Assignee: Semiconductor Diagnostics, Inc.
    Inventors: Jacek J. Lagowski, Piotr Edelman, Frank Gossett, Nick Kochey, Alexandre Savtchouk
  • Publication number: 20040057497
    Abstract: Techniques for measuring a contact potential difference of a sample at an elevated temperature using a probe designed for room temperature measurement are disclosed. In such measurements, probe damage by excessive heating can be prevented without any probe modifications to include probe cooling. This can be achieved by minimizing the time the probe spends in close proximity to the heated sample. Furthermore, the effect of probe heating by the sample on the probe reading can be corrected by including an additional contact potential difference measurement of a reference plate kept at room temperature in the measurement cycle.
    Type: Application
    Filed: September 24, 2002
    Publication date: March 25, 2004
    Inventors: Jacek J. Lagowski, Piotr Edelman, Frank Gossett, Nick Kochey, Alexandre Savtchouk
  • Patent number: 6037797
    Abstract: A method of determining charge associated with traps present in a semiconductor oxide interface is described. The method includes the steps of depositing a dose of charge over a surface of the oxide and measuring a resultant value of surface potential barrier at the portion of the surface. From the measured value of surface charge and deposited charge dose a value of charge associated with the interface trap is determined. The method also includes determining space charge corresponding to the measured surface potential barrier of the portion of the substrate. With the determined space charge and known deposited charge the interface trapped charge is determined by noting that the change in interface trapped charge is related to the negative of the changes in space charge and deposited charge.
    Type: Grant
    Filed: July 11, 1997
    Date of Patent: March 14, 2000
    Assignee: Semiconductor Diagnostics, Inc.
    Inventors: Jacek Lagowski, Piotr Edelman, Marshall D. Wilson
  • Patent number: 5773989
    Abstract: A method and apparatus for measuring the concentration of mobile ions in the oxide layer of a semiconductor wafer from the contact potential shift caused by ion drift across the oxide that includes depositing charge (e.g., using a corona discharge device) on the surface of the oxide and heating the wafer to allow mobile ions in the oxide (especially Na.sup.+) to drift. The difference in the contact potential measured before and after heating provides an indication of the mobile ion concentration in the oxide layer.
    Type: Grant
    Filed: July 14, 1995
    Date of Patent: June 30, 1998
    Assignees: University of South Florida, Semiconductor Diagnostics, Inc.
    Inventors: Piotr Edelman, Andrew M. Hoff, Lubek Jastrzebski, Jacek Lagowski
  • Patent number: 5663657
    Abstract: Minority carrier diffusion lengths, especially long diffusion lengths that exceed the thickness of the wafer, are determined accurately and conveniently using techniques that limit errors due to lateral carrier diffusion, surface reflectivity, temperature variations, and inherent limitations in standard computation techniques that assume a diffusion length shorter than the wafer thickness. In particular embodiments, a probe is provided that senses the photovoltage in an area spaced from the edge of the illuminated region to provide a measurement substantially free of error from lateral carrier diffusion. The probe may also measure surface reflectivity simultaneously with measurement of photovoltage. Reflectivity correction is particularly beneficial in the analysis of wafers with dielectric coatings.
    Type: Grant
    Filed: September 26, 1994
    Date of Patent: September 2, 1997
    Assignees: University of South Florida, Semiconductor Diagostics, Inc.
    Inventors: Jacek Lagowski, Lubek Jastrzebski, Andrzej Kontkiewicz, Piotr Edelman