Patents by Inventor Piotr Luniewski

Piotr Luniewski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device including a circuit to compensate for parasitic inductance
    Patent number: 9793889
    Abstract: A semiconductor device includes a first transistor, a second transistor coupled in parallel with the first transistor, and a first parasitic inductance between an emitter of the first transistor and an emitter of the second transistor. The semiconductor device includes a first circuit configured to provide a first gate driver signal to the first transistor based on a common driver signal and a second circuit configured to provide a second gate driver signal to the second transistor based on the common driver signal. The first circuit and the second circuit are configured to compensate for a voltage drop across the first parasitic inductance such that the first gate driver signal and the second gate driver signal are in phase with and at the same magnitude as the common driver signal.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: October 17, 2017
    Assignee: Infineon Technologies AG
    Inventors: Reinhold Bayerer, Piotr Luniewski
  • SEMICONDUCTOR DEVICE INCLUDING A CIRCUIT TO COMPENSATE FOR PARASITIC INDUCTANCE
    Publication number: 20120235663
    Abstract: A semiconductor device includes a first transistor, a second transistor coupled in parallel with the first transistor, and a first parasitic inductance between an emitter of the first transistor and an emitter of the second transistor. The semiconductor device includes a first circuit configured to provide a first gate driver signal to the first transistor based on a common driver signal and a second circuit configured to provide a second gate driver signal to the second transistor based on the common driver signal. The first circuit and the second circuit are configured to compensate for a voltage drop across the first parasitic inductance such that the first gate driver signal and the second gate driver signal are in phase with and at the same magnitude as the common driver signal.
    Type: Application
    Filed: March 15, 2011
    Publication date: September 20, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Reinhold Bayerer, Piotr Luniewski