Patents by Inventor Pitamber Shukla

Pitamber Shukla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11031085
    Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The memory structure includes one or more planes of non-volatile memory cells. Each plane is divided into a plurality of partial planes. The control circuit is configured to write to and read from the memory cells by writing a partial page into a particular partial plane and reading the partial page from the particular partial plane using a set of parameters optimized for the particular partial plane.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: June 8, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Mohan V Dunga, Pitamber Shukla
  • Patent number: 10971240
    Abstract: The storage device comprises a non-volatile memory coupled to a controller. The controller is configured to determine a first programming voltage by performing at least one program-verify iteration on a first word line using a voltage value which starts as a predetermined first initial voltage and is sequentially increased by a first voltage step amount following each failure to successfully program until the programming is completed. The controller is also configured to determine a second initial programming voltage by decreasing the first programming voltage by a second voltage step amount. The controller is further configured to perform at least one program-verify iteration on a second word line of the plurality of word lines using a voltage value which starts as the second initial programming voltage and is increased by the first voltage step amount following each sequential failure to successfully program until the programming is completed.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: April 6, 2021
    Inventors: Mohan Dunga, Pitamber Shukla
  • Patent number: 10878926
    Abstract: A high-performance write operation to program data to a group of non-volatile memory cells may be completed in response to applying a single programming pulse to the group. Programming of the cells may be verified (and/or corrected) after completion of the command. Verifying programming of the cells may comprise identifying under-programmed cells, and applying an additional programming pulse to the identified cells. The under-programmed cells may comprise cells within an under-program range below a target level. The under-program range may be determined based on a threshold voltage distribution of the cells in response to applying the single programming pulse.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: December 29, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Pitamber Shukla, Mohan Dunga, Anubhav Khandelwal
  • Patent number: 10790031
    Abstract: A data storage system performs operations including receiving a data read command corresponding to a first memory cell; determining whether the first memory cell is in a first read condition; if the first memory cell is in the first read condition: applying a first voltage level to the first memory cell, the first voltage level being a predetermined voltage level corresponding to a read operation for memory cells in the first read condition; and sensing a first level of current, or lack thereof, through the first memory cell during application of the first voltage level to the first memory cell; and if the first memory cell is not in the first read condition: applying a second voltage level to the first memory cell, the second voltage level being a voltage level corresponding to a read operation for memory cells in a read condition other than the first read condition.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: September 29, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Piyush Sagdeo, Chris Yip, Sourabh Sankule, Pitamber Shukla, Anubhav Khandelwal, Mohan Dunga, Niles Yang
  • Publication number: 20200303010
    Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The memory structure includes one or more planes of non-volatile memory cells. Each plane is divided into a plurality of partial planes. The control circuit is configured to write to and read from the memory cells by writing a partial page into a particular partial plane and reading the partial page from the particular partial plane using a set of parameters optimized for the particular partial plane.
    Type: Application
    Filed: June 9, 2020
    Publication date: September 24, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Mohan V. Dunga, Pitamber Shukla
  • Patent number: 10755798
    Abstract: Recovering data from a faulty memory block in a memory system. Various methods include: reading a target word line in a memory block to obtain a first data; determining the first data has an uncorrectable error; and then adjust bias parameters of a first group of neighboring word lines within the memory block, where adjusting bias parameters creates a first adjusted bias parameters; and reading the target word line using the adjusted bias parameters to obtain second data from the target word line. The method also includes determining the second data has a second uncorrectable error; and then adjusting bias parameters of a second group of lines within the memory block, where adjusting the bias parameters of the second group creates second adjusted bias parameters; and reading the target word line using the first and second adjusted bias parameters to obtain a third data from the target word line.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: August 25, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Niles Yang, Pitamber Shukla, Mohan Dunga
  • Patent number: 10741251
    Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The memory structure includes one or more planes of non-volatile memory cells. Each plane is divided into a plurality of partial planes. The control circuit is configured to write to and read from the memory cells by writing a partial page into a particular partial plane and reading the partial page from the particular partial plane using a set of parameters optimized for the particular partial plane.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: August 11, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Mohan V Dunga, Pitamber Shukla
  • Patent number: 10714169
    Abstract: A non-volatile memory system and corresponding method of operation are provided. The system includes non-volatile memory cells, each retaining a threshold voltage within a threshold window. The non-volatile memory cells include multi-bit cells each configured to store a plurality of bits of data with the threshold window partitioned into bands each having a band width. The bands include a lowest band denoting an erased state and increasing bands. A control circuit programs a first set of the data into the multi-bit cells in a single-bit mode using first target states being one of the erased state and a tight intermediate state having a distribution of the threshold voltage no wider than the band width of one of the increasing bands. The control circuit also programs a second set of the data into the multi-bit cells in a multi-bit mode with each of the multi-bit cells storing the plurality of bits.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: July 14, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Phil Reusswig, Pitamber Shukla, Sarath Puthenthermadam, Mohan Dunga, Sahil Sharma, Rohit Sehgal, Niles Yang
  • Publication number: 20200194094
    Abstract: Recovering data from a faulty memory block in a memory system. Various methods include: reading a target word line in a memory block to obtain a first data; determining the first data has an uncorrectable error; and then adjust bias parameters of a first group of neighboring word lines within the memory block, where adjusting bias parameters creates a first adjusted bias parameters; and reading the target word line using the adjusted bias parameters to obtain second data from the target word line. The method also includes determining the second data has a second uncorrectable error; and then adjusting bias parameters of a second group of lines within the memory block, where adjusting the bias parameters of the second group creates second adjusted bias parameters; and reading the target word line using the first and second adjusted bias parameters to obtain a third data from the target word line.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: Niles Yang, Pitamber Shukla, Mohan Dunga
  • Patent number: 10636493
    Abstract: Dynamic modification of health metrics for data blocks in non-volatile storage media based on erase operation loop counts. In one implementation, a method includes iteratively erasing a block of non-volatile storage media until a count of non-erasable bits satisfies criteria comprising an allowable non-erasable bits parameter, and determining that a number of iterations needed to erase the block exceeds a threshold number of iterations. The method further includes, in response to the number of iterations exceeding the threshold number of iterations, increasing the allowable non-erasable bits parameter for a subsequent erasure of the block.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: April 28, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Niles Yang, Pitamber Shukla
  • Patent number: 10559366
    Abstract: Apparatuses, systems, methods, and computer program products for dynamically determining boundary word line voltage shift are presented. An apparatus includes an array of non-volatile memory cells and a controller. A controller includes a trigger detection component that is configured to detect a trigger condition associated with a last programmed word line of a partially programmed erase block of an array of non-volatile memory cells. A controller includes a voltage component that is configured to determine a read voltage threshold for a last programmed word line of a partially programmed erase block in response to a trigger condition. A controller includes a voltage shift component that is configured to calculate, dynamically, a read voltage threshold shift for a last programmed word line based on a determined read voltage threshold for the last programmed word line and a baseline read voltage threshold.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: February 11, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Zhenlei Shen, Pitamber Shukla, Philip Reusswig, Niles N. Yang, Anubhav Khandelwal
  • Publication number: 20200035313
    Abstract: A high-performance write operation to program data to a group of non-volatile memory cells may be completed in response to applying a single programming pulse to the group. Programming of the cells may be verified (and/or corrected) after completion of the command. Verifying programming of the cells may comprise identifying under-programmed cells, and applying an additional programming pulse to the identified cells. The under-programmed cells may comprise cells within an under-program range below a target level. The under-program range may be determined based on a threshold voltage distribution of the cells in response to applying the single programming pulse.
    Type: Application
    Filed: October 2, 2019
    Publication date: January 30, 2020
    Inventors: Pitamber Shukla, Mohan Dunga, Anubhav Khandelwal
  • Patent number: 10541031
    Abstract: A program circuit may two-dimensionally program data into cells by applying different selected bit line or channel voltages to different bit lines or channels located in different bit line zones of a block during a program operation. The block may be further separated or divided into word line zones. The program circuit may adjust the different bit line or channel voltages as it programs in different word line zones of the block. In accordance with the two-dimensional programming, the program circuit may perform single-pulse program-only SLC program operations.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: January 21, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Mohan Vamsi Dunga, Piyush Dak, Pitamber Shukla
  • Publication number: 20200005875
    Abstract: Dynamic modification of health metrics for data blocks in non-volatile storage media based on erase operation loop counts. In one implementation, a method includes iteratively erasing a block of non-volatile storage media until a count of non-erasable bits satisfies criteria comprising an allowable non-erasable bits parameter, and determining that a number of iterations needed to erase the block exceeds a threshold number of iterations. The method further includes, in response to the number of iterations exceeding the threshold number of iterations, increasing the allowable non-erasable bits parameter for a subsequent erasure of the block.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 2, 2020
    Inventors: Niles Yang, Pitamber Shukla
  • Publication number: 20190385680
    Abstract: A program circuit may two-dimensionally program data into cells by applying different selected bit line or channel voltages to different bit lines or channels located in different bit line zones of a block during a program operation. The block may be further separated or divided into word line zones. The program circuit may adjust the different bit line or channel voltages as it programs in different word line zones of the block. In accordance with the two-dimensional programming, the program circuit may perform single-pulse program-only SLC program operations.
    Type: Application
    Filed: June 15, 2018
    Publication date: December 19, 2019
    Applicant: SanDisk Technologies LLC
    Inventors: Mohan Vamsi Dunga, Piyush Dak, Pitamber Shukla
  • Patent number: 10460816
    Abstract: A high-performance write operation to program data to a group of non-volatile memory cells may be completed in response to applying a single programming pulse to the group. Programming of the cells may be verified (and/or corrected) after completion of the command. Verifying programming of the cells may comprise identifying under-programmed cells, and applying an additional programming pulse to the identified cells. The under-programmed cells may comprise cells within an under-program range below a target level. The under-program range may be determined based on a threshold voltage distribution of the cells in response to applying the single programming pulse.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: October 29, 2019
    Assignee: Sandisk Technologies LLC
    Inventors: Pitamber Shukla, Mohan Dunga, Anubhav Khandelwal
  • Patent number: 10460814
    Abstract: Embodiments of the present disclosure generally relate to non-volatile memory devices, such as flash memory, and sensing operation methods including locking out high conduction current memory cells of the memory devices. In one embodiment, a method of sensing a plurality of memory cells in an array includes conducting a lower page read of one or more demarcation threshold voltages. Each memory cell is programmable to a threshold voltage corresponding to one of multiple memory states. A middle page read of one or more demarcation threshold voltages is conducted. Memory cells identified from the lower page read are selectively locked out during the middle page read. An upper page read of one or more demarcation threshold voltages is conducted. Memory cells identified from a prior page read are selectively locked out during the upper page read.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: October 29, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Piyush Dak, Mohan Vamsi Dunga, Pitamber Shukla
  • Publication number: 20190304550
    Abstract: Apparatuses, systems, methods, and computer program products for dynamically determining boundary word line voltage shift are presented. An apparatus includes an array of non-volatile memory cells and a controller. A controller includes a trigger detection component that is configured to detect a trigger condition associated with a last programmed word line of a partially programmed erase block of an array of non-volatile memory cells. A controller includes a voltage component that is configured to determine a read voltage threshold for a last programmed word line of a partially programmed erase block in response to a trigger condition. A controller includes a voltage shift component that is configured to calculate, dynamically, a read voltage threshold shift for a last programmed word line based on a determined read voltage threshold for the last programmed word line and a baseline read voltage threshold.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Applicant: Western Digital Technologies, Inc.
    Inventors: ZHENLEI SHEN, PITAMBER SHUKLA, PHILIP REUSSWIG, NILES N. YANG, ANUBHAV KHANDELWAL
  • Patent number: 10354736
    Abstract: The present disclosure is directed to a device, a method, and a non-transitory computer readable medium for determining a level of uncertainty of programmed states of memory cells. In one aspect, a memory device includes memory cells, an uncertainty prediction circuit coupled to the memory cells, and a data conversion circuit coupled to the memory cells. The uncertainty prediction circuit is configured to determine, from a subset of the memory cells coupled to a word line, a number of memory cells having a predetermined state. The data conversion circuit is configured to apply a data conversion to a portion of data stored by the subset of the memory cells, in response to the uncertainty prediction circuit determining that the number of memory cells is between a first threshold and a second threshold.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: July 16, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Nian Niles Yang, Pitamber Shukla
  • Publication number: 20190180822
    Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The memory structure includes one or more planes of non-volatile memory cells. Each plane is divided into a plurality of partial planes. The control circuit is configured to write to and read from the memory cells by writing a partial page into a particular partial plane and reading the partial page from the particular partial plane using a set of parameters optimized for the particular partial plane.
    Type: Application
    Filed: April 17, 2018
    Publication date: June 13, 2019
    Applicant: SanDisk Technologies LLC
    Inventors: Mohan V Dunga, Pitamber Shukla