Abstract: A storage system determines that it is undergoing intensive reads by a host, which can occur, for example, when the storage system is being used to play a video game for a prolonged period of time. As performing a conventional read scrub operation in that situation can result in a decrease in performance, the storage system can instead use a targeted read scrub operation to reduce the impact on host read performance. The targeted read scrub operation can take the form, for example, of a periodic read scan on areas of the memory that are not part of the intensive host read, random read scans on neighboring wordlines where only a single state is read, and/or a passive read scan where acceptable but risky pages are marked for relocation.

Abstract: A storage system determines that it is undergoing intensive reads by a host, which can occur, for example, when the storage system is being used to play a video game for a prolonged period of time. As performing a conventional read scrub operation in that situation can result in a decrease in performance, the storage system can instead use a targeted read scrub operation to reduce the impact on host read performance. The targeted read scrub operation can take the form, for example, of a periodic read scan on areas of the memory that are not part of the intensive host read, random read scans on neighboring wordlines where only a single state is read, and/or a passive read scan where acceptable but risky pages are marked for relocation.

Abstract: A method and apparatus for dynamically determining when, or how often, to do a read scan operation on a solid-state storage drive. One solution adjusts a read scan interval as part of performing a read scan operation. First, a bit error rate is determined for one of a plurality of storage blocks of a non-volatile memory array. Then, a cross temperature metric for the storage block is determined. A read scan interval is changed in response to the cross temperature metric satisfying a cross temperature threshold. Then, data in the storage block is relocated to a free storage block in response to the bit error rate satisfying a relocation threshold.

Abstract: A storage system and method for boundary wordline data retention handling are provided. In one embodiment, the storage system includes a memory having a single-level cell (SLC) block and a multi-level cell (MLC) block. The system determines if the boundary wordline in the MLC block has a data retention problem (e.g., by determining how long it has been since the boundary wordline was programmed). To address the data retention problem, the storage system can copy data from a wordline in the SLC block that corresponds to the boundary wordline in the MLC block to a wordline in another SLC block prior to de-committing the data in the SLC block. Alternatively, the storage system can reprogram the data in the boundary wordline using a double fine programing technique.

Abstract: A memory apparatus and method of operation is provided. The apparatus includes a plurality of memory cells coupled to a control circuit. The control circuit is configured to receive data indicating a data state for each memory cell of a set of memory cells of the plurality of memory cells and program, in multiple programming loops, the set of memory cells according to the data indicating the data state for each memory cell of the set of memory cells. The control circuit is further configured to determine that the programming of the set of memory cells is in a last programming loop of the multiple programming loops and in response to the determination, receive data indicating a data state for each memory cell of another set of memory cells of the plurality of memory cells.

Abstract: The present disclosure generally relates to identifying read failures that enhanced post write/read (EPWR) would normally miss. After the last logical word line has been written, additional stress is added to each word line. More specifically, the gate bias channel pass read voltage for all unselected word lines is increased, the gate bias on dummy and selected gate word lines is increased, the gate bias on the selected word line is increased, and a pulse read occurs. The increasing and reading occurs for each word line. Thereafter, EPWR occurs. Due to the increasing and reading for every word line, additional read failures are discovered than would otherwise be discovered with EPWR alone.

Abstract: A memory apparatus and method of operation is provided. The apparatus includes a plurality of memory cells coupled to a control circuit. The control circuit is configured to receive data indicating a data state for each memory cell of a set of memory cells of the plurality of memory cells and program, in multiple programming loops, the set of memory cells according to the data indicating the data state for each memory cell of the set of memory cells. The control circuit is further configured to determine that the programming of the set of memory cells is in a last programming loop of the multiple programming loops and in response to the determination, receive data indicating a data state for each memory cell of another set of memory cells of the plurality of memory cells.

Abstract: A method and apparatus for dynamically determining when, or how often, to do a read scan operation on a solid-state storage drive. One solution adjusts a read scan interval as part of performing a read scan operation. First, a bit error rate is determined for one of a plurality of storage blocks of a non-volatile memory array. Then, a cross temperature metric for the storage block is determined. A read scan interval is changed in response to the cross temperature metric satisfying a cross temperature threshold. Then, data in the storage block is relocated to a free storage block in response to the bit error rate satisfying a relocation threshold.

Abstract: A storage system and method for boundary wordline data retention handling are provided. In one embodiment, the storage system includes a memory having a single-level cell (SLC) block and a multi-level cell (MLC) block. The system determines if the boundary wordline in the MLC block has a data retention problem (e.g., by determining how long it has been since the boundary wordline was programmed). To address the data retention problem, the storage system can copy data from a wordline in the SLC block that corresponds to the boundary wordline in the MLC block to a wordline in another SLC block prior to de-committing the data in the SLC block. Alternatively, the storage system can reprogram the data in the boundary wordline using a double fine programing technique.

Abstract: A method of operating a storage device, including; performing, by a non-volatile memory, an erase operation on a block of memory in the non-volatile memory, where the non-volatile memory is coupled to a controller; receiving, by the non-volatile memory, a host-transaction within a first time period, where, the non-volatile memory is coupled to a host device; and suspending, by the non-volatile memory, an erase operation in response to receiving the host-transaction by: determining the erase operation has completed a charge phase; and suspending the erase operation during a pulse phase of the erase operation. The method additionally includes the non-volatile memory maintaining a loop counter and a pulse counter, where: the loop counter increments in response to completion of an erase loop, and the pulse counter increments in response to completion of an erase pulse, where the erase pulse is applied during a pulse phase of the erase operation.

Abstract: A method of operating a storage device, including; performing, by a non-volatile memory, an erase operation on a block of memory in the non-volatile memory, where the non-volatile memory is coupled to a controller; receiving, by the non-volatile memory, a host-transaction within a first time period, where, the non-volatile memory is coupled to a host device; and suspending, by the non-volatile memory, an erase operation in response to receiving the host-transaction by: determining the erase operation has completed a charge phase; and suspending the erase operation during a pulse phase of the erase operation. The method additionally includes the non-volatile memory maintaining a loop counter and a pulse counter, where: the loop counter increments in response to completion of an erase loop, and the pulse counter increments in response to completion of an erase pulse, where the erase pulse is applied during a pulse phase of the erase operation.

Abstract: A circuit configured to dynamically adjust data transfer speeds for a non-volatile memory die interface. The circuit includes an initialization circuit, a control circuit, a switch circuit, and a read-write circuit. The initialization circuit is configured to load multi-level cell settings that configure a memory interface for transfer of data for storage cells configured to store more than one bit per storage cell. The control circuit is configured to receive a read command that references single-level storage cells of a memory die. The switch circuit is configured to switch settings for the memory interface from the multi-level cell settings to single level cell settings, in response to receiving the read command. The read-write circuit is configured to read data for the read command from the memory die using the single level cell settings.

Abstract: Non-volatile memory and processes for reprogramming data posing a potential reliability concern are provided. A process is provided for distinguishing between cross-temperature effects and read disturb effects as part of determining whether to perform a maintenance operation such as reprogramming. A process is provided that compensates for cross-temperature effects while testing to determine whether to perform a maintenance operation. Applying temperature compensation attempts to remove cross-temperature effects so that testing accurately detects whether read disturb has occurred, without the effects of temperature. By reducing cross-temperature effects, maintenance operations can be more accurately scheduled for memory that has experienced read disturb, as opposed to cross-temperature effects.

Abstract: Non-volatile memory and processes for reprogramming data posing a potential reliability concern are provided. A process is provided for distinguishing between cross-temperature effects and read disturb effects as part of determining whether to perform a maintenance operation such as reprogramming. A process is provided that compensates for cross-temperature effects while testing to determine whether to perform a maintenance operation. Applying temperature compensation attempts to remove cross-temperature effects so that testing accurately detects whether read disturb has occurred, without the effects of temperature. By reducing cross-temperature effects, maintenance operations can be more accurately scheduled for memory that has experienced read disturb, as opposed to cross-temperature effects.