Patents by Inventor Piyush C. Patel
Piyush C. Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9128868Abstract: A system to improve error code decoding with retries may include a processing unit that requests data packets, and a queue to hold the data packets for the processing unit. The system may also include a decoder to determine a processing time for each data packet in the queue based upon any errors in each data packet, and if the processing time for a particular data packet is greater than a threshold, then to renew any requests for the data packets that are in the queue.Type: GrantFiled: January 31, 2008Date of Patent: September 8, 2015Assignee: International Business Machines CorporationInventors: Luis A. Lastras-Montano, Piyush C. Patel, Eric E. Retter, Barry M. Trager, Michael R. Trombley, Shmuel Winograd
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Patent number: 8352806Abstract: A system to improve memory failure management may include memory, and an error control decoder to determine failures in the memory. The system may also include an agent that may monitor failures in the memory. The system may further include a table where the error control decoder may record the failures, and where the agent can read and write to.Type: GrantFiled: January 31, 2008Date of Patent: January 8, 2013Assignee: International Business Machines CorporationInventors: Marc A. Gollub, Luis A. Lastras-Montano, Piyush C. Patel, Eric E. Retter, Barry M. Trager, Shmuel Winograd, Kenneth L. Wright
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Patent number: 8347037Abstract: A data processing system includes a processor core having an associated upper level cache and a lower level victim cache. In response to a memory access request of the processor core that specifies a non-modifying access to a target coherency granule, a determination is made whether the memory access request hits or misses in a directory of the lower level victim cache. In response to determining that the memory access request hits in the lower level victim cache in a data-valid coherence state, the lower level victim cache provides the target coherency granule of the memory access request to the upper level cache. The lower level victim cache preserves the target coherency granule in the lower level victim cache in a shared coherence state if the memory access request is of a first type and invalidates the target coherency granule if the memory access request is of a second type.Type: GrantFiled: October 22, 2008Date of Patent: January 1, 2013Assignee: International Business Machines CorporationInventors: Guy L. Guthrie, Thomas L. Jeremiah, William L. McNeil, Piyush C. Patel, William J. Starke, Jeffrey A. Stuecheli
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Patent number: 8181094Abstract: A system to improve error correction includes a fast decoder to process data packets until the fast decoder finds an uncorrectable error in a data packet at which point a request for at least two data packets is generated. The system also includes a slow decoder to correct the uncorrectable error in a data packet based upon the at least two data packets.Type: GrantFiled: January 31, 2008Date of Patent: May 15, 2012Assignee: International Business Machines CorporationInventors: Luis A. Lastras-Montano, Piyush C. Patel, Eric E. Retter, Barry M. Trager, Michael R. Trombley, Shmuel Winograd, Kenneth L. Wright
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Patent number: 8135752Abstract: Techniques and articles of manufacture are provided comprising computer readable programs that, when executed on the computer, cause the computer to delete a leaf from a patricia tree having leaf keys and pattern search control blocks containing a prefix and either an end-of-trail leaf or a pointer to another of the pattern search control blocks, by placing each of the prefixes in a tree prefix table; searching for a key in the tree; searching for the key in the prefix table if the tree searching does not find the key in the tree; confirming that the key is deleted if the key is not found in the prefix table; deleting the key from one of the pattern search control blocks; and collapsing the patricia tree by eliminating the left most pattern search control block from the patricia tree if the patricia tree searching finds the key.Type: GrantFiled: January 8, 2009Date of Patent: March 13, 2012Assignee: International Business Machines CorporationInventors: Claude Basso, Jean L. Calvignac, Gordon T. Davis, Marco Heddes, Piyush C. Patel, Steven R. Perrin, Grayson W. Randall, Sonia K. Rovner
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Patent number: 8117397Abstract: A cache memory includes a cache array including a plurality of congruence classes each containing a plurality of cache lines, where each cache line belongs to one of multiple classes which include at least a first class and a second class. The cache memory also includes a cache directory of the cache array that indicates class membership. The cache memory further includes a cache controller that selects a victim cache line for eviction from a congruence class. If the congruence class contains a cache line belonging to the second class, the cache controller preferentially selects as the victim cache line a cache line of the congruence class belonging to the second class based upon access order. If the congruence class contains no cache line belonging to the second class, the cache controller selects as the victim cache line a cache line belonging to the first class based upon access order.Type: GrantFiled: December 16, 2008Date of Patent: February 14, 2012Assignee: International Business Machines CorporationInventors: Guy L. Guthrie, Thomas L. Jeremiah, William L. McNeil, Piyush C. Patel, William J. Starke, Jeffrey A. Stuecheli
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Patent number: 8005869Abstract: Method for compressing search tree structures used in rule classification is provided. The method includes classifying packets based on filter rules, compressing a tree structure comprising multiple levels of single bit test nodes and leaf nodes, storing the compressed tree structure in a first memory structure of a storage such that the multiple levels of single bit test nodes and leaf nodes can be accessed from the first memory structure through a single memory access of the storage, collecting single bit test nodes of the tree structure that are in a lowest level of the tree structure, storing only the collected single bit test nodes within a second memory structure of the storage that is contiguous to the first memory structure, collecting leaf nodes of the tree structure, and storing only the collected leaf nodes within a third memory structure of the storage that is contiguous to second memory structure.Type: GrantFiled: March 14, 2008Date of Patent: August 23, 2011Assignee: International Business Machines CorporationInventors: Everett A. Corl, Jr., Gordon T. Davis, Marco Heddes, Piyush C. Patel, Ravinder K. Sabhikhi
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Patent number: 7941390Abstract: The present invention relates to a system for managing a plurality of multi-field classification rules. The system provides a first table that includes a plurality of entries corresponding to a plurality of rules relating to an ingress context and a second table that includes a plurality of entries corresponding to a plurality of rules relating to an egress context. The system also includes a network processor for classifying packets of information, wherein the network processor is programmed to utilize the first table and the second table to identify any rules relating to the ingress context and any one rules relating to the egress context that match a search key.Type: GrantFiled: June 20, 2008Date of Patent: May 10, 2011Assignee: International Business Machines CorporationInventors: Everett A. Corl, Jr., Gordon T. Davis, Marco C. Heddes, Piyush C. Patel, Ravinder K. Sabhikhi
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Publication number: 20100293437Abstract: A system to improve memory failure management may include memory, and an error control decoder to determine failures in the memory. The system may also include an agent that may monitor failures in the memory. The system may further include a table where the error control decoder may record the failures, and where the agent can read and write to.Type: ApplicationFiled: January 31, 2008Publication date: November 18, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Marc A. Gollub, Luis A. Lastras-Montano, Piyush C. Patel, Eric E. Retter, Barry M. Trager, Shmuel Winograd, Kenneth L. Wright
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Publication number: 20100293438Abstract: A system to improve error correction may include a fast decoder to process data packets until the fast decoder finds an uncorrectable error in a data packet at which point a request for at least two data packets is generated. The system may also include a slow decoder to possibly correct the uncorrectable error in a data packet based upon the at least two data packets.Type: ApplicationFiled: January 31, 2008Publication date: November 18, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Luis A. Lastras-Montano, Piyush C. Patel, Eric E. Retter, Barry M. Trager, Michael R. Trombley, Shmuel Winograd, Kenneth L. Wright
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Publication number: 20100287436Abstract: A system to improve error code decoding with retries may include a processing unit that requests data packets, and a queue to hold the data packets for the processing unit. The system may also include a decoder to determine a processing time for each data packet in the queue based upon any errors in each data packet, and if the processing time for a particular data packet is greater than a threshold, then to renew any requests for the data packets that are in the queue.Type: ApplicationFiled: January 31, 2008Publication date: November 11, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Luis A. Lastras-Montano, Piyush C. Patel, Eric E. Retter, Barry M. Trager, Michael R. Trombley, Shmuel Winogard
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Patent number: 7752155Abstract: The present invention relates to a system and computer-readable medium for storing a plurality of multi-field classification rules in a computer system. Each multi-field classification rule includes a rule specification that itself includes a plurality of fields and a plurality of field definitions corresponding to the fields. The method of the present invention includes providing a virtual rule table, where the table stores a plurality of field definitions, and for each of the plurality of multi-field classification rules, compressing the rule specification by replacing at least one field definition with an associated index into the virtual rule table. The method also includes storing each of the compressed rule specifications and the virtual rule table in a shared segment of memory.Type: GrantFiled: July 29, 2008Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Everett A. Corl, Jr., Gordon T. Davis, Marco C. Heddes, Piyush C. Patel, Ravinder K. Sabhikhi
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Publication number: 20100153650Abstract: A cache memory includes a cache array including a plurality of congruence classes each containing a plurality of cache lines, where each cache line belongs to one of multiple classes which include at least a first class and a second class. The cache memory also includes a cache directory of the cache array that indicates class membership. The cache memory further includes a cache controller that selects a victim cache line for eviction from a congruence class. If the congruence class contains a cache line belonging to the second class, the cache controller preferentially selects as the victim cache line a cache line of the congruence class belonging to the second class based upon access order. If the congruence class contains no cache line belonging to the second class, the cache controller selects as the victim cache line a cache line belonging to the first class based upon access order.Type: ApplicationFiled: December 16, 2008Publication date: June 17, 2010Applicant: International Business Machines CorporationInventors: Guy L. Guthrie, Thomas L. Jeremiah, William L. McNeil, Piyush C. Patel, William J. Starke, Jeffrey A. Stuecheli
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Publication number: 20100100682Abstract: A data processing system includes a processor core having an associated upper level cache and a lower level victim cache. In response to a memory access request of the processor core that specifies a non-modifying access to a target coherency granule, a determination is made whether the memory access request hits or misses in a directory of the lower level victim cache. In response to determining that the memory access request hits in the lower level victim cache in a data-valid coherence state, the lower level victim cache provides the target coherency granule of the memory access request to the upper level cache. The lower level victim cache preserves the target coherency granule in the lower level victim cache in a shared coherence state if the memory access request is of a first type and invalidates the target coherency granule if the memory access request is of a second type.Type: ApplicationFiled: October 22, 2008Publication date: April 22, 2010Applicant: International Business Machines CorporationInventors: Guy L. Guthrie, Thomas L. Jeremiah, William L. McNeil, Piyush C. Patel, William J. Starke, Jeffrey A. Stuecheli
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Patent number: 7702630Abstract: A method and apparatus are used for finding the longest prefix match in a variable length prefix search when searching a direct table within a routing table structure of a network processor. The search through the routing table structure is expedited by hashing a first segment of an internet protocol address with a virtual private network number followed by concatenating the unhashed bits of the IP address to the result of the hash operation to form an input key. Patterns are compared a bit at a time until an exact match or the best match is found. The search is conducted in a search tree that provides that the matching results will be the best possible match.Type: GrantFiled: February 14, 2006Date of Patent: April 20, 2010Assignee: International Business Machines CorporationInventors: Claude Basso, Jean L. Calvignac, Gordon T. Davis, Piyush C. Patel
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Publication number: 20090125535Abstract: Techniques and articles of manufacture are provided comprising computer readable programs that, when executed on the computer, cause the computer to delete a leaf from a Patricia tree having a direct table and a plurality of PSCB's which decode portions of the pattern of a leaf in the tree without shutting down the functioning of the tree. A leaf having a pattern is identified as a leaf to be deleted. Using the pattern, the tree is walked to identify the location of the leaf to be deleted. The leaf to be deleted is identified and deleted, and any relevant PSCB modified, if necessary. The technique also is applicable to deleting a prefix of a prefix.Type: ApplicationFiled: January 8, 2009Publication date: May 14, 2009Applicant: International Business Machines CorporationInventors: Claude Basso, Jean L. Calvignac, Gordon T. Davis, Marco Heddes, Piyush C. Patel, Steven R. Perrin, Grayson W. Randall, Sonia K. Rovner
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Patent number: 7490101Abstract: A technique is provided to delete a leaf from a Patricia tree having a direct table and a plurality of PSCB's which decode portions of the pattern of a leaf in the tree without shutting down the functioning of the tree. A leaf having a pattern is identified as a leaf to be deleted. Using the pattern, the tree is walked to identify the location of the leaf to be deleted. The leaf to be deleted is identified and deleted, and any relevant PSCB modified, if necessary. The technique also is applicable to deleting a prefix of a prefix.Type: GrantFiled: August 4, 2006Date of Patent: February 10, 2009Assignee: International Business Machines CorporationInventors: Claude Basso, Jean L. Calvignac, Gordon T. Davis, Marco Heddes, Piyush C. Patel, Steven R. Perrin, Grayson W. Randall, Sonia K. Rovner
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Publication number: 20080285454Abstract: The present invention relates to a system for storing a plurality of multi-field classification rules in a computer system. Each multi-field classification rule includes a rule specification that itself includes a plurality of fields and a plurality of field definitions corresponding to the fields.Type: ApplicationFiled: July 29, 2008Publication date: November 20, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Everett A. CORL, JR., Gordon T. Davis, Marco C. Heddes, Piyush C. Patel, Ravinder K. Sabhikhi
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Patent number: 7454396Abstract: The present invention relates to a method for storing a plurality of multi-field classification rules in a computer system. Each multi-field classification rule includes a rule specification that itself includes a plurality of fields and a plurality of field definitions corresponding to the fields. The method of the present invention includes providing a virtual rule table, where the table stores a plurality of field definitions, and for each of the plurality of multi-field classification rules, compressing the rule specification by replacing at least one field definition with an associated index into the virtual rule table. The method also includes storing each of the compressed rule specifications and the virtual rule table in a shared segment of memory.Type: GrantFiled: April 27, 2004Date of Patent: November 18, 2008Assignee: International Business Machines CorporationInventors: Everett A. Corl, Jr., Gordon T. Davis, Marco Heddes, Piyush C. Patel, Ravinder K. Sabhikhi
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Publication number: 20080249973Abstract: The present invention relates to a system for managing a plurality of multi-field classification rules. The system provides a first table that includes a plurality of entries corresponding to a plurality of rules relating to an ingress context and a second table that includes a plurality of entries corresponding to a plurality of rules relating to an egress context. The system also includes a network processor for classifying packets of information, wherein the network processor is programmed to utilize the first table and the second table to identify any rules relating to the ingress context and any one rules relating to the egress context that match a search key.Type: ApplicationFiled: June 20, 2008Publication date: October 9, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Everett A. Corl, Gordon T. Davis, Marco Heddes, Piyush C. Patel, Ravinder K. Sabhikhi