Patents by Inventor Piyush Chunilal Patel
Piyush Chunilal Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8495272Abstract: A computer implemented method, bus switching system, and computer usable program code are provided for saving bus switching power and reducing noise. A request for data is received from a requester by a first cache. A determination is made as to whether the data is stored on the first cache. Responsive to determining that the data is stored on the first cache, a bus in a plurality of buses is identified on which to return the data forming an identified bus. The data is sent to the requester on the identified bus. A logical state is initiated on the remaining plurality of buses stemming from the first cache in order to save bus switching power and reducing noise.Type: GrantFiled: November 29, 2006Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Piyush Chunilal Patel, Deepak K. Singh
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Patent number: 7984038Abstract: Novel data structures, methods and apparatus for finding the longest prefix match search when searching tables with variable length patterns or prefixes. To find the exact match or the best matching prefix, patterns have to be compared a bit at a time until the exact or first match is found. This requires “n” number of comparisons or memory accesses to identify the closest matching pattern. The trees are built in such a way that the matching result is guaranteed to be a best match, whether it is an exact match or a longest prefix match. Using the trail of all the birds and associated prefix lengths enables determination of the correct prefix result from the trail. By construction, the search tree provides the best matching prefix at or after the first compare during walking of the trail or tree.Type: GrantFiled: April 15, 2008Date of Patent: July 19, 2011Assignee: International Business Machines CorporationInventors: Brian Mitchell Bass, Jean Louis Calvignac, Marco C. Heddes, Antonios Maragkos, Piyush Chunilal Patel, Michael Steven Siegel, Fabrice Jean Verplanken
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Publication number: 20080222116Abstract: Novel data structures, methods and apparatus for finding the longest prefix match search when searching tables with variable length patterns or prefixes. To find the exact match or the best matching prefix, patterns have to be compared a bit at a time until the exact or first match is found. This requires “n” number of comparisons or memory accesses to identify the closest matching pattern. The trees are built in such a way that the matching result is guaranteed to be a best match, whether it is an exact match or a longest prefix match. Using the trail of all the birds and associated prefix lengths enables determination of the correct prefix result from the trail. By construction, the search tree provides the best matching prefix at or after the first compare during walking of the trail or tree.Type: ApplicationFiled: April 15, 2008Publication date: September 11, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian Mitchell Bass, Jean Louis Calvignac, Marco C. Heddes, Antonios Maragkos, Piyush Chunilal Patel, Michael Steven Siegel, Fabrice Jean Verplanken
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Patent number: 7383244Abstract: Novel data structures, methods and apparatus for finding the longest prefix match search when searching tables with variable length patterns or prefixes. To find the exact match or the best matching prefix, patterns have to be compared a bit at a time until the exact or first: match is found. This requires “n” number of comparisons or memory accesses to identify the closest matching pattern. The trees are built in such a way that the matching result is guaranteed to be a best match, whether it is an exact match or a longest prefix match. Using the trail of all the birds and associated prefix lengths enables determination of the correct prefix result from the trail. By construction, the search tree provides the best matching prefix at or after the first compare during walking of the trail or tree.Type: GrantFiled: January 28, 2005Date of Patent: June 3, 2008Assignee: International Business Machines CorporationInventors: Brian Mitchell Bass, Jean Louis Calvignac, Marco C. Heddes, Antonios Maragkos, Piyush Chunilal Patel, Michael Steven Siegel, Fabrice Jean Verplanken
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Publication number: 20080126666Abstract: A computer implemented method, bus switching system, and computer usable program code are provided for saving bus switching power and reducing noise. A request for data is received from a requester by a first cache. A determination is made as to whether the data is stored on the first cache. Responsive to determining that the data is stored on the first cache, a bus in a plurality of buses is identified on which to return the data forming an identified bus. The data is sent to the requester on the identified bus. A logical state is initiated on the remaining plurality of buses stemming from the first cache in order to save bus switching power and reducing noise.Type: ApplicationFiled: November 29, 2006Publication date: May 29, 2008Inventors: Piyush Chunilal Patel, Deepak K. Singh
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Patent number: 7139753Abstract: Novel data structures, methods and apparatus for finding a full match between a search pattern and a pattern stored in a leaf of the search tree. A key is input, a hash function is performed on the key, a direct table (DT) is accessed, and a tree is walked through pattern search control blocks (PSCBs) until reaching a leaf. The search mechanism uses a set of data structures that can be located in a few registers and regular memory, and then used to build a Patricia tree structure that can be manipulated by a relatively simple hardware macro. Both keys and corresponding information needed for retrieval are stored in the Patricia tree structure. The hash function provides an n->n mapping of the bits of the key to the bits of the hash key. The data structure that is used to store the hash key and the related information in the tree is called a leaf. Each leaf corresponds to a single key that matches exactly with the input key. The leaf contains the key as well as additional information.Type: GrantFiled: August 28, 2003Date of Patent: November 21, 2006Assignee: International Business Machines CorporationInventors: Brian Mitchell Bass, Jean Louis Calvignac, Marco C. Heddes, Antonios Maragkos, Piyush Chunilal Patel, Michael Steven Siegel, Fabrice Jean Verplanken
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Patent number: 7120630Abstract: Novel data structures, methods and apparatus for finding a full match between a search pattern and a pattern stored in a leaf of the search tree. A key is input, a hash function is performed on the key, a direct table (DT) is accessed, and a tree is walked through pattern search control blocks (PSCBs) until reaching a leaf. The search mechanism uses a set of data structures that can be located in a few registers and regular memory, and then used to build a Patricia tree structure that can be manipulated by a relatively simple hardware macro. Both keys and corresponding information needed for retrieval are stored in the Patricia tree structure. The hash function provides an n->n mapping of the bits of the key to the bits of the hash key.Type: GrantFiled: August 28, 2003Date of Patent: October 10, 2006Assignee: International Business Machines CorporationInventors: Brian Mitchell Bass, Jean Louis Calvignac, Marco C. Heddes, Antonios Maragkos, Piyush Chunilal Patel, Michael Steven Siegel, Fabrice Jean Verplanken
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Patent number: 7107265Abstract: Novel data structures, methods and apparatus for a Software Managed Tree (SMT) which provides a mechanism to create tree structures that follow a search mechanism defined by a control point processor. The search mechanism does not require storage on the previous pointer and uses only a forward pointer along with a next bit or group of bits to test thereby reducing storage space for nodes. The search mechanism processes multiple filter rules for an application without requiring multiple searches and also allows various filter rules to be chained. Two patterns of the same length are stored in each leaf to define a range compare. A compare at the end operation is either a compare under range or a compare under mask. In a compare under range, the input key is checked to determine if it is in the range defined by the two patterns. In a compare under mask, the bits in the input key are compared with the bits in a first leaf pattern under a mask specified in a second leaf pattern.Type: GrantFiled: April 6, 2000Date of Patent: September 12, 2006Assignee: International Business Machines CorporationInventors: Jean Louis Calvignac, Marco C. Heddes, Clark Debs Jeffries, Piyush Chunilal Patel, Mark Anthony Rinaldi
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Patent number: 7036125Abstract: A method, system and computer program product for eliminating memory corruption when performing multi-threaded tree operations. A network processor may receive a command to perform a tree operation on a tree on one or more of multiple threads. Upon performing the requested tree operation, the network processor may lock one or more resources during a portion of the execution of the requested tree operation using one or more semaphores. A semaphore may refer to a flag used to indicate whether to “lock” or make available the resource associated with the semaphore. Locking may refer to preventing the resource from being available to other threads. Hence, by locking one or more resources during a portion of the tree operation, memory corruption may be eliminated in a multiple thread system while preventing these resources from being used by other threads for a minimal amount of time.Type: GrantFiled: August 13, 2002Date of Patent: April 25, 2006Assignee: International Business Machines CorporationInventors: Claude Basso, Matthew William Kilpatrick Brown, Gordon Taylor Davis, Marco Heddes, Piyush Chunilal Patel, Grayson Warren Randall, Sonia Kiang Rovner, Colin Beaton Verrilli
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Patent number: 6947931Abstract: Novel data structures, methods and apparatus for finding the longest prefix match search when searching tables with variable length patterns or prefixes. To find the exact match or the best matching prefix, patterns have to be compared a bit at a time until the exact or first match is found. This requires “n” number of comparisons or memory accesses to identify the closest matching pattern. The trees are built in such a way that the matching result is guaranteed to be a best match, whether it is an exact match or a longest prefix match. Using the trail of all the birds and associated prefix lengths enables determination of the correct prefix result from the trail. By construction, the search tree provides the best matching prefix at or after the first compare during walking of the trail or tree.Type: GrantFiled: April 6, 2000Date of Patent: September 20, 2005Assignee: International Business Machines CorporationInventors: Brian Mitchell Bass, Jean Louis Calvignac, Marco C. Heddes, Antonios Maragkos, Piyush Chunilal Patel, Michael Steven Siegel, Fabrice Jean Verplanken
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Patent number: 6928162Abstract: A method and system for providing a hash and a complement of the hash for an item in a computer system are disclosed. The method and system include providing a plurality of components from the item. The plurality of components include a first component and a last component. Each of the plurality of components includes a particular number of bits. The method and system also include cascading the plurality of components through at least one XOR to provide a plurality of resultants. The plurality of resultants includes a first resultant and a final resultant. The final resultant includes only the last component. The first resultant includes an XOR of the first component and remaining cascaded components of the plurality of components. The method and system also include applying an invertible hash function and an invertible hash function complement to at least the first resultant to provide the hash. The complement of the hash includes the plurality of resultants except the first resultant.Type: GrantFiled: April 7, 2000Date of Patent: August 9, 2005Assignee: International Business Machines CorporationInventors: Marco C. Heddes, Clark Debs Jeffries, Piyush Chunilal Patel
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Patent number: 6785278Abstract: Methods systems and computer program products are provided for hashing address values that exhibit banding in a plurality of regions of an address space defined by at least two segments of the address values, by performing at least one of a translation and a rotation of the at least two segments to thereby map the at least two segments from the plurality of regions to one of the plurality of regions.Type: GrantFiled: December 10, 1998Date of Patent: August 31, 2004Assignee: International Business Machines CorporationInventors: Jean Louis Calvignac, Marco C. Heddes, Clark Debs Jeffries, Ross Boyd Leavens, Gerald Arnold Marin, Piyush Chunilal Patel, Atef Omar Zaghloul
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Patent number: 6769033Abstract: A network processor useful in network switch apparatus and methods of operating such a processor in which data flow handling and flexibility is enhanced by the cooperation of an embedded processor complex with a suite of peripherals, all formed on a common semiconductor substrate. The interface processors provide data paths for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate, while storage of transiting data flow portions is provided by memory peripherals and interfaces to external memory elements.Type: GrantFiled: August 27, 1999Date of Patent: July 27, 2004Assignee: International Business Machines CorporationInventors: Brian Mitchell Bass, Jean Louis Calvignac, Anthony Matteo Gallo, Marco C. Heddes, Ross Boyd Leavens, Piyush Chunilal Patel, Mark Anthony Rinaldi, Michael Steven Siegel, Fabrice Jean Verplanken
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Publication number: 20040032867Abstract: A method, system and computer program product for eliminating memory corruption when performing multi-threaded tree operations. A network processor may receive a command to perform a tree operation on a tree on one or more of multiple threads. Upon performing the requested tree operation, the network processor may lock one or more resources during a portion of the execution of the requested tree operation using one or more semaphores. A semaphore may refer to a flag used to indicate whether to “lock” or make available the resource associated with the semaphore. Locking may refer to preventing the resource from being available to other threads. Hence, by locking one or more resources during a portion of the tree operation, memory corruption may be eliminated in a multiple thread system while preventing these resources from being used by other threads for a minimal amount of time.Type: ApplicationFiled: August 13, 2002Publication date: February 19, 2004Applicant: International Business Machines CorporationInventors: Claude Basso, Matthew William Kilpatrick Brown, Gordon Taylor Davis, Marco Heddes, Piyush Chunilal Patel, Grayson Warren Randall, Sonia Kiang Rovner, Colin Beaton Verrilli
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Patent number: 6675163Abstract: Novel data structures, methods and apparatus for finding a full match between a search pattern and a pattern stored in a leaf of the search tree. A key is input, a hash function is performed on the key, a direct table (DT) is accessed, and a tree is walked through pattern search control blocks (PSCBs) until reaching a leaf. The search mechanism uses a set of data structures that can be located in a few registers and regular memory, and then used to build a Patricia tree structure that can be manipulated by a relatively simple hardware macro. Both keys and corresponding information needed for retrieval are stored in the Patricia tree structure. The hash function provides an n→n mapping of the bits of the key to the bits of the hash key. The data structure that is used to store the hash key and the related information in the tree is called a leaf. Each leaf corresponds to a single key that matches exactly with the input key. The leaf contains the key as well as additional information.Type: GrantFiled: April 6, 2000Date of Patent: January 6, 2004Assignee: International Business Machines CorporationInventors: Brian Mitchell Bass, Jean Louis Calvignac, Marco C. Heddes, Antonios Maragkos, Piyush Chunilal Patel, Michael Steven Siegel, Fabrice Jean Verplanken
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Patent number: 6463500Abstract: A method is provided for utilizing a memory system which allows for the fast and efficient writing and reading of objects to and from diverse memory chips. A computer system and memory system complex according to method is also provided. The invention defines objects in terms of “shapes.” The shape of an object is defined by two parameters: “Width” and “Height.” Memory system memory chips may comprise sets of different kinds of memory modules which vary in terms of access speed, latency and memory width, such as for example DRAM or SRAM memory modules. The Height of an object denotes the number of consecutive address locations at which the object is stored on a memory module. The Width of an object denotes the number of memory modules at which the object is stored. An advantage of the invention is that objects are defined in terms of “sub-objects” optimized for the memory system memory modules.Type: GrantFiled: January 4, 2000Date of Patent: October 8, 2002Assignee: International Business Machines CorporationInventors: Marco C. Heddes, Piyush Chunilal Patel, Mark Anthony Rinaldi
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Patent number: 6460120Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a plurality of memory elements and a plurality of interface processors formed on a semiconductor substrate. The memory elements and interface processors together form a network processor capable of cooperating with other elements in executing instructions directing the flow of data in a network. Access to the memory elements is controlled in a particular manner and under operative rules which provide controlled multiple accesses of the plurality of memory elements by the plurality of processors.Type: GrantFiled: August 27, 1999Date of Patent: October 1, 2002Assignee: International Business Machines CorporationInventors: Brian Mitchell Bass, Jean Louis Calvignac, Marco C. Heddes, Piyush Chunilal Patel, Juan Guillermo Revilla, Michael Steven Siegel, Fabrice Jean Verplanken
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Patent number: 6453386Abstract: A method and system for performing aging of a memory in a computer system is disclosed. The memory contains a plurality of items. The method and system include purging the memory of a portion of the plurality of items each time an epoch equal to an aging variable has expired. The method and system further include providing the aging variable for a new epoch based on a performance of the memory in a previous epoch, including the aging variable of the previous epoch.Type: GrantFiled: September 30, 1999Date of Patent: September 17, 2002Assignee: International Business Machines CorporationInventors: Clark Debs Jeffries, Piyush Chunilal Patel, Gail Irene Woodland
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Publication number: 20020099855Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a plurality of memory elements and a plurality of interface processors formed on a semiconductor substrate. The memory elements and interface processors together form a network processor capable of cooperating with other elements in executing instructions directing the flow of data in a network. Access to the memory elements is controlled in a particular manner and under operative rules which provide controlled multiple accesses of the plurality of memory elements by the plurality of processors.Type: ApplicationFiled: August 27, 1999Publication date: July 25, 2002Inventors: BRIAN MITCHELL BASS, MARCO C. HEDDES, PIYUSH CHUNILAL PATEL, JUAN GUILLERMO REVILLA, MICHAEL STEVEN SIEGEL, FABRICE JEAN VERPLANKEN
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Patent number: 6298340Abstract: A classification system includes a software managed tree testing bits from a key which labels an item. The bits are chosen by application of the Choice Bit Algorithm to the Rules in a Database of Rules. A controller including logic parses an unknown Key for bits to be tested in the decision nodes of a binary tree. Tests dictated by the tree are conducted in a predetermined way until all but one Rule from the database or all but a few Rules from the database are eliminated from consideration, whereupon the Key is fully tested by the one remaining Rule or in a lattice constructed of the remaining plurality of Rules, to determine an action to enforce on the item. Certain compare tests are used in the binary tree for the case that otherwise identical or similar rules are applied to integer ranges of key values which do not fall upon power of 2 boundaries.Type: GrantFiled: May 14, 1999Date of Patent: October 2, 2001Assignee: International Business Machines CorporationInventors: Jean Louis Calvignac, Everett Arthur Corl, Jr., Anthony Matteo Gallo, Marco C. Heddes, Clark Debs Jeffries, Piyush Chunilal Patel, Mark Anthony Rinaldi, Colin Beaton Verrilli