Patents by Inventor Piyush Dak
Piyush Dak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10984876Abstract: Various methods include receiving, by a controller, a temperature reading of a memory array, the temperature reading includes a temperature value; determining the temperature value is below a first threshold; in response, modifying a duration of a verify cycle of a write operation to create a modified verify cycle; then programming a first data into the memory array using the write operation that uses the modified verify cycle. Methods additionally include receiving a second temperature reading of the memory array, the second temperature reading includes a second temperature value; determining the second temperature value is below a second threshold, in response, decreasing the duration of a verify cycle of a verify cycle to create a second verify cycle, where the second verify cycle is shorter than the modified verify cycle; and then programming a second data into the memory array using the write operation that uses the second verify cycle.Type: GrantFiled: June 19, 2019Date of Patent: April 20, 2021Assignee: SanDiskTechnologies LLCInventors: Piyush Dak, Mohan Dunga, Chao Qin, Muhammad Masuduzzaman, Xiang Yang
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Publication number: 20200402594Abstract: Various methods include receiving, by a controller, a temperature reading of a memory array, the temperature reading includes a temperature value; determining the temperature value is below a first threshold; in response, modifying a duration of a verify cycle of a write operation to create a modified verify cycle; then programming a first data into the memory array using the write operation that uses the modified verify cycle. Methods additionally include receiving a second temperature reading of the memory array, the second temperature reading includes a second temperature value; determining the second temperature value is below a second threshold, in response, decreasing the duration of a verify cycle of a verify cycle to create a second verify cycle, where the second verify cycle is shorter than the modified verify cycle; and then programming a second data into the memory array using the write operation that uses the second verify cycle.Type: ApplicationFiled: June 19, 2019Publication date: December 24, 2020Applicant: SanDisk Technologies LLCInventors: Piyush Dak, Mohan Dunga, Chao Qin, Muhammad Masuduzzaman, Xiang Yang
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Patent number: 10825827Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and an I/O interface. A portion of the memory die is used as a pool capacitor for the I/O interface.Type: GrantFiled: September 25, 2018Date of Patent: November 3, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Mohan Dunga, James Kai, Venkatesh P. Ramachandra, Piyush Dak, Luisa Lin, Masaaki Higashitani
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Patent number: 10818685Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and an I/O interface. A portion of the memory die is used as a pool capacitor for the I/O interface.Type: GrantFiled: September 25, 2018Date of Patent: October 27, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Mohan Dunga, James Kai, Venkatesh P. Ramachandra, Piyush Dak, Luisa Lin, Masaaki Higashitani
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Publication number: 20200248230Abstract: A process and device for electrostatically controlling an ionic environment in a droplet, such as in a droplet-based platform including polymerase-chain reaction (PCR) applications. The process includes providing a chip that comprises at least a pair of electrodes, placing a salt-containing droplet on the chip, and then applying a bias across the electrodes to accumulate ions near surfaces of the electrodes, thereby depleting a bulk salt concentration in regions of the droplet away from the electrodes.Type: ApplicationFiled: September 4, 2019Publication date: August 6, 2020Applicant: PURDUE RESEARCH FOUNDATIONInventors: Muhammad Ashraful Alam, Piyush Dak
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Patent number: 10559370Abstract: A circuit includes a detection circuit configured to determine a capacitance delay (RC-delay) in an initial stage of a read or program operation and to adjust timing for detecting data in a subsequent stage, or portion of a stage, of the same read or programming operation. In particular, during a program operation a detection circuit may be configured to detect a pre-charge time for a bit line and adjust a timing of subsequent verify stages of the bit line during the same program operation based on the detected pre-charge time. Additionally, a word line circuit may be configured to detect a pre-charge time for a word line during an initial stage of a read operation and adjust read timing for a subsequent portion of the same read stage, or subsequent read stage of the read operation based on the detected word line pre-charge time.Type: GrantFiled: March 22, 2018Date of Patent: February 11, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Xiang Yang, Piyush Dak, Wei Zhao, Huai-Yuan Tseng, Deepanshu Dutta, Mohan Dunga
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Patent number: 10541031Abstract: A program circuit may two-dimensionally program data into cells by applying different selected bit line or channel voltages to different bit lines or channels located in different bit line zones of a block during a program operation. The block may be further separated or divided into word line zones. The program circuit may adjust the different bit line or channel voltages as it programs in different word line zones of the block. In accordance with the two-dimensional programming, the program circuit may perform single-pulse program-only SLC program operations.Type: GrantFiled: June 15, 2018Date of Patent: January 21, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Mohan Vamsi Dunga, Piyush Dak, Pitamber Shukla
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Publication number: 20200013794Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and an I/O interface. A portion of the memory die is used as a pool capacitor for the I/O interface.Type: ApplicationFiled: September 25, 2018Publication date: January 9, 2020Applicant: SANDISK TECHNOLOGIES LLCInventors: Mohan Dunga, James Kai, Venkatesh P. Ramachandra, Piyush Dak, Luisa Lin, Masaaki Higashitani
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Publication number: 20200013795Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and an I/O interface. A portion of the memory die is used as a pool capacitor for the I/O interface.Type: ApplicationFiled: September 25, 2018Publication date: January 9, 2020Applicant: SANDISK TECHNOLOGIES LLCInventors: Mohan Dunga, James Kai, Venkatesh P. Ramachandra, Piyush Dak, Luisa Lin, Masaaki Higashitani
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Publication number: 20190385680Abstract: A program circuit may two-dimensionally program data into cells by applying different selected bit line or channel voltages to different bit lines or channels located in different bit line zones of a block during a program operation. The block may be further separated or divided into word line zones. The program circuit may adjust the different bit line or channel voltages as it programs in different word line zones of the block. In accordance with the two-dimensional programming, the program circuit may perform single-pulse program-only SLC program operations.Type: ApplicationFiled: June 15, 2018Publication date: December 19, 2019Applicant: SanDisk Technologies LLCInventors: Mohan Vamsi Dunga, Piyush Dak, Pitamber Shukla
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Patent number: 10460814Abstract: Embodiments of the present disclosure generally relate to non-volatile memory devices, such as flash memory, and sensing operation methods including locking out high conduction current memory cells of the memory devices. In one embodiment, a method of sensing a plurality of memory cells in an array includes conducting a lower page read of one or more demarcation threshold voltages. Each memory cell is programmable to a threshold voltage corresponding to one of multiple memory states. A middle page read of one or more demarcation threshold voltages is conducted. Memory cells identified from the lower page read are selectively locked out during the middle page read. An upper page read of one or more demarcation threshold voltages is conducted. Memory cells identified from a prior page read are selectively locked out during the upper page read.Type: GrantFiled: December 12, 2017Date of Patent: October 29, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Piyush Dak, Mohan Vamsi Dunga, Pitamber Shukla
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Publication number: 20190295669Abstract: A circuit includes a detection circuit configured to determine a capacitance delay (RC-delay) in an initial stage of a read or program operation and to adjust timing for detecting data in a subsequent stage, or portion of a stage, of the same read or programing operation. In particular, during a program operation a detection circuit may be configured to detect a pre-charge time for a bit line and adjust a timing of subsequent verify stages of the bit line during the same program operation based on the detected pre-charge time. Additionally, a word line circuit may be configured to detect a pre-charge time for a word line during an initial stage of a read operation and adjust read timing for a subsequent portion of the same read stage, or subsequent read stage of the read operation based on the detected word line pre-charge time.Type: ApplicationFiled: March 22, 2018Publication date: September 26, 2019Applicant: SanDisk Technologies LLCInventors: Xiang Yang, Piyush Dak, Wei Zhao, Huai-Yuan Tseng, Deepanshu Dutta, Mohan Dunga
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Publication number: 20190180823Abstract: Embodiments of the present disclosure generally relate to non-volatile memory devices, such as flash memory, and sensing operation methods including locking out high conduction current memory cells of the memory devices. In one embodiment, a method of sensing a plurality of memory cells in an array includes conducting a lower page read of one or more demarcation threshold voltages. Each memory cell is programmable to a threshold voltage corresponding to one of multiple memory states. A middle page read of one or more demarcation threshold voltages is conducted. Memory cells identified from the lower page read are selectively locked out during the middle page read. An upper page read of one or more demarcation threshold voltages is conducted. Memory cells identified from a prior page read are selectively locked out during the upper page read.Type: ApplicationFiled: December 12, 2017Publication date: June 13, 2019Inventors: Piyush DAK, Mohan Vamsi DUNGA, Pitamber SHUKLA
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Publication number: 20160251699Abstract: A process and device for electrostatically controlling an ionic environment in a droplet, such as in a droplet-based platform including polymerase-chain reaction (PCR) applications. The process includes providing a chip that comprises at least a pair of electrodes, placing a salt-containing droplet on the chip, and then applying a bias across the electrodes to accumulate ions near surfaces of the electrodes, thereby depleting a bulk salt concentration in regions of the droplet away from the electrodes.Type: ApplicationFiled: February 26, 2016Publication date: September 1, 2016Applicant: PURDUE RESEARCH FOUNDATIONInventors: Muhammad Ashraful Alam, Piyush Dak